DLL Locking State Detector for Jitter-Tolerant Phase Control
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Solution Overview
Problem
DLL circuits in semiconductor ICs face instability due to frequent changes in the locking state signal caused by jitter in the external clock signal, leading to unstable internal clock generation and reduced operational stability.
Innovation Solution
A locking state detector that compares reference and feedback clock signals to generate distinct phase difference signals, enabling the locking state signal only when the phase difference is below a first range and disabling it when it exceeds a wider second range, thereby maintaining a stable operation mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the locking state signal is disabled whenever phase difference exceeds a predetermined range, then phase synchronization is maintained, but the locking state signal is frequently changed by jitter causing unstable operation
Solution Approach 1:
The phase difference range is segmented into multiple distinct ranges: a first phase difference range for normal operation, a second phase difference range wider than the first for jitter tolerance, and a third phase difference range for actual lock loss detection. This segmentation allows the system to distinguish between temporary jitter effects and genuine phase synchronization failures, preventing unnecessary locking state changes while maintaining precise phase control when needed.
2Measurement precision
If the phase difference threshold is set narrowly to detect synchronization accurately, then phase control precision is improved, but jitter causes frequent false lock loss detections
Solution Approach 1:
The system dynamically adjusts the phase difference threshold based on the detected phase difference magnitude. When phase difference falls within the first range, a narrower threshold is applied for precise control. When phase difference enters the second range but remains below the third range, the system recognizes this as jitter and maintains the current locking state without false re-triggering. Only when phase difference exceeds the third range does the system respond with lock loss detection.
3Stability of the object's composition
If the locking state signal responds immediately to phase difference changes, then phase synchronization is maintained, but the DLL circuit frequently changes operation mode reducing stability
Solution Approach 1:
The system prepares for potential jitter effects by establishing a hysteresis mechanism through multiple phase difference ranges before actual lock loss occurs. The second phase difference range acts as a cushion zone that absorbs jitter variations, preventing them from triggering immediate locking state changes. This beforehand cushioning ensures that only significant and sustained phase differences beyond the third range cause operation mode changes, maintaining stability while preserving necessary phase control responsiveness.
Data Source
AI summary
A locking state detector includes a phase comparing unit configured to compare a reference clock signal and a feedback clock signal to generate a first phase difference distinction signal to distinguish a first phase difference range, and a second phase difference distinction signal to distinguish a second phase difference range wider than the first phase difference range, and a locking state setting unit configured to generate a locking state signal in response to the first phase difference distinction signal and the second phase difference distinction signal.