DLL Loop Count Detection for Faster Clock Synchronization

The patent applies preliminary action by using a measure-controlled delay (MCD) circuit to perform initial delay measurement and setup before the DLL circuit begins its synchronization process. The MCD circuit pre-configures the delay elements based on initial measurements, allowing the DLL to start from a near-locked state rather than from scratch, thereby reducing the number of clock cycles required for full synchronization.

The patent implements feedback mechanisms where the DLL circuit continuously monitors phase differences between clock signals and adjusts delay element settings accordingly. The measure-controlled delay circuit provides feedback based on measured delay values, allowing the system to compensate for manufacturing variations and environmental factors such as temperature and voltage changes, thereby maintaining synchronization accuracy without requiring overly complex predetermined compensation schemes.

The patent applies dynamics by making the delay configuration adaptive rather than static. The MCD circuit dynamically adjusts delay settings based on initial measurements, and the DLL circuit further dynamically adjusts delays during operation based on phase error feedback. This dynamic approach allows the system to achieve fast initial lock capability while minimizing the total delay required for lock conditions by optimizing delay values in real-time rather than using fixed conservative delay settings.