DLL Majority Filtering for Stable Delay Line Locking
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Solution Overview
Problem
Conventional Delay Locked Loops (DLLs) in memory devices suffer from oscillations caused by external clock jitter, phase detection circuit noise, and process-voltage-temperature variations, leading to increased power consumption and longer synchronization times.
Innovation Solution
The implementation of a high-speed, low-power DLL with an oscillation filter and majority filter to detect and dampen delay line control signal oscillations, ensuring stable synchronization by comparing current and buffered control signals and delaying shifts until a predetermined trend is established.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DLL is used to synchronize internal clock with external clock, then synchronization function is achieved, but oscillation occurs due to external clock jitter and phase detection noise, leading to extended locking time and increased power consumption
Solution Approach 1:
The patent introduces an oscillation filter as an intermediary component between the phase detector and delay line. This filter detects oscillations in the delay line control signal and prevents them from affecting the delay line, thereby eliminating the source of extended locking time while maintaining synchronization stability
Solution Approach 2:
The patent implements a feedback mechanism where the oscillation filter continuously monitors the delay line control signal and provides corrective action by blocking oscillatory components. This feedback loop enables the system to maintain stable synchronization without the extended locking time caused by oscillations
2Reliability
If conventional DLL tracks oscillating external clock signal, then clock synchronization is maintained, but extra shifts to delay lines occur, consuming additional power
Solution Approach 1:
The oscillation filter serves as a mediator that allows legitimate clock synchronization signals to pass through while blocking harmful oscillatory signals. This selective filtering maintains clock synchronization reliability while preventing the extra delay line shifts that would otherwise consume additional power
3Reliability
If DLL delay line is adjusted to compensate for oscillation, then synchronization is maintained, but the locking process takes longer duration
Solution Approach 1:
The patent extracts the oscillation filtering function as a separate stage before the delay line adjustment. By removing oscillations from the control signal beforehand, the delay line can lock quickly without needing to compensate for oscillations, thereby reducing locking duration while maintaining synchronization reliability
Data Source
AI summary
Control signal oscillation filtering circuits, delay locked loops, clock synchronization methods and devices and systems incorporating the control signal oscillation filtering circuits are described. An oscillation filtering circuit includes a first oscillation filter configured to filter oscillations and a majority filter configured to average filter an output of a phase detector and generate in response thereto control signals to an adjustable delay line.