DLL Majority Filtering for Faster Stable Clock Lock
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Solution Overview
Problem
Conventional Delay Locked Loops (DLLs) in memory devices suffer from oscillations caused by external clock jitter, phase detection circuit noise, and process-voltage-temperature variations, leading to increased power consumption and longer synchronization times at high frequencies.
Innovation Solution
A high-speed, low-power DLL design incorporating an oscillation filter and a majority filter to detect and dampen delay line control signal oscillations, ensuring stable synchronization by comparing current and buffered control signals and delaying shift commands until a predetermined count is reached.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DLL is used to synchronize internal clock with external clock, then clock synchronization is achieved, but oscillation occurs causing extended lock time and increased power consumption
Solution Approach 1:
The patent applies preliminary action by detecting oscillation conditions before they cause extended lock time. The phase detector continuously monitors for oscillation patterns in the delay line control signals, and when oscillation is detected, the controller proactively adjusts the delay line to eliminate the oscillation condition before it significantly impacts lock acquisition time.
Solution Approach 2:
The patent implements feedback through a closed-loop system where the phase detector monitors the difference between external and internal clock signals, and the controller adjusts the delay line based on this feedback. Additionally, a secondary feedback mechanism detects oscillation in the control signals and provides corrective feedback to eliminate the oscillation, thereby reducing lock time and improving stability.
2Reliability
If DLL tracks oscillating external clock signal, then synchronization is maintained, but power consumption increases due to extra delay line shifts
Solution Approach 1:
The patent applies partial action by making delay line adjustments only when necessary. Instead of continuously shifting the delay line to track every oscillation, the system detects oscillation patterns and makes targeted adjustments only when oscillation is detected, thereby maintaining synchronization while minimizing unnecessary power-consuming shifts.
Solution Approach 2:
The feedback mechanism monitors the phase difference and oscillation conditions, providing control signals to the delay line only when adjustment is needed. This feedback-based control prevents excessive or unnecessary delay line shifts, thereby reducing power consumption while maintaining reliable clock synchronization.
3Reliability
If delay line control signals are adjusted to track clock oscillation, then synchronization is maintained, but device complexity increases
Solution Approach 1:
The patent uses preliminary action by implementing an oscillation detection mechanism that identifies oscillation conditions early in the synchronization process. This allows the system to take corrective action before oscillation significantly impacts performance, simplifying the overall control logic compared to systems that must continuously compensate for oscillation.
Solution Approach 2:
The patent introduces an intermediary oscillation detection and control mechanism between the phase detector and the delay line. This intermediary layer analyzes control signals for oscillation patterns and provides smoothed, oscillation-free control signals to the delay line, thereby maintaining synchronization stability without requiring complex direct control mechanisms.
Data Source
AI summary
Control signal oscillation filtering circuits, delay-locked loops, clock synchronization methods and devices and systems incorporating control signal oscillation filtering circuits are described. An oscillation filtering circuit includes a first oscillation filter configured to filter oscillations and a majority filter configured to average filter an output of a phase detector and generate in response thereto control signals to an adjustable delay line.