DLL Measure Initialization for Faster, More Accurate Clock Locking
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Solution Overview
Problem
Conventional delay locked loops (DLLs) in synchronous integrated circuits face challenges in achieving accurate and fast synchronization of internal and external clock signals, especially at higher frequencies, due to significant phase shifts and the need for additional circuitry which increases power consumption and chip size.
Innovation Solution
The proposed DLL circuit employs a measure initialization mode that directly applies inherent delays to the coarse delay line during initialization, allowing for faster locking by minimizing initial delay settings and reducing the reliance on separate model delay circuits, thereby enhancing the accuracy and speed of phase locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional DLL circuits use separate model delay circuits to compensate for inherent delays, then phase locking accuracy can be improved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the separate model delay circuit from the DLL structure. Instead of using a dedicated model delay circuit to compensate for inherent delays, the invention incorporates delay compensation directly into the main delay line structure, removing the need for separate compensation circuitry while maintaining phase locking accuracy.
Solution Approach 2:
The patent merges the delay compensation function with the main delay line. The coarse delay line is designed to include built-in compensation for inherent delays in the DLL circuitry, combining what were previously separate functions (delay generation and delay compensation) into a single integrated structure.
2Measurement precision
If conventional DLL circuits use extensive delay adjustments and model delay circuits, then synchronization accuracy can be improved, but chip size increases
Solution Approach 1:
The patent removes the model delay circuit component entirely, extracting its delay compensation function and integrating it into the coarse delay line structure. This elimination of separate circuitry directly reduces the chip area required while maintaining synchronization accuracy.
Solution Approach 2:
The coarse delay line is designed to serve multiple functions simultaneously: it provides coarse delay adjustment and inherently compensates for DLL circuitry delays. This multi-functionality eliminates the need for separate model delay circuits, reducing overall chip size while maintaining accuracy.
3Measurement precision
If conventional DLL circuits perform multiple delay adjustments before locking, then phase locking accuracy can be improved, but locking time increases
Solution Approach 1:
The patent implements preliminary action by designing the coarse delay line with built-in delay compensation that is already configured to account for inherent DLL delays. This preliminary configuration eliminates the need for multiple iterative adjustments, allowing the DLL to achieve accurate phase locking faster by starting from a pre-compensated state.
Solution Approach 2:
The invention skips the iterative adjustment process by incorporating delay compensation directly into the delay line structure. Instead of performing multiple delay adjustments to compensate for inherent delays, the system rushes through to accurate phase locking in a single adjustment phase, significantly reducing locking time.
4Measurement precision
If conventional DLL circuits use additional circuitry for delay measurement and compensation, then measurement precision can be improved, but power consumption increases
Solution Approach 1:
The patent extracts and removes the separate model delay circuit and associated control logic, eliminating the additional power consumption these components would generate. The delay measurement and compensation functions are integrated into the main delay line structure, reducing overall power usage while maintaining measurement precision.
Solution Approach 2:
The patent merges the delay measurement and compensation functions into the coarse delay line structure. By combining these functions into a single integrated structure rather than using separate circuits, the invention reduces the total number of active components and their associated power consumption while maintaining delay measurement accuracy.
Data Source
AI summary
A clock generator having a delay locked loop and a delay control circuit. The delay locked loop receives an input clock signal and adjusts an adjustable delay circuit to generate an output clock signal that is synchronized with received input clock signal. The delay control circuit coupled to the delay locked loop generates a control signal to initialize the delay measure operation to adjust the adjustable delay circuit, after comparing the phase difference of the input clock signal and the output clock signal. The delay control circuit further generates a start measure control signal to start measuring a delay applied to the measurement signal propagating through the adjustable delay circuit, and generates a stop measure control signal to stop the delay measurement of the measurement signal. The delay adjustment of the delay locked loop is then adjusted to apply the delay measurement when synchronizing the input and output clock signals.