DLL-Based Memory Interface for QDR2 SRAM Skew Reduction
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Solution Overview
Problem
High-speed QDR2 SRAM memory interface designs face challenges in minimizing data skew, clock generation, and testing due to pseudo-random nature of synthesis and optimization tools, leading to difficulties in achieving high data rates and reliable operation at frequencies like 333 MHz.
Innovation Solution
A memory interface circuit with a clock phase providing circuit and single to double data rate converting circuits, utilizing a delay locked loop to generate accurate clock phases and reduce pin-to-pin skews, and a master-slave DLL for reliable echo clock translation, allowing for controlled timing and reduced reliance on differential clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fully-synthesized memory interface design is used, then ease of implementation and foundry portability are improved, but high data rates above 200 MHz cannot be achieved
Solution Approach 1:
The memory interface is divided into two distinct parts: a fully-synthesized control logic portion that ensures ease of implementation and portability, and a solidified (hand-designed) I/O buffer interface portion that optimizes for high-speed operation. This segmentation allows each part to be optimized independently for its specific requirements.
Solution Approach 2:
Different design approaches are applied to different parts of the interface: standard cell libraries and synthesis tools are used for the control logic where ease of implementation is paramount, while custom hand-designed circuitry is used for the I/O buffers where maximizing data rate is the priority. This local quality approach ensures optimal performance in each region.
2Adaptability or versatility
If standard cell libraries are used for synthesis, then foundry portability is improved, but timing precision at high frequencies deteriorates
Solution Approach 1:
The interface design separates concerns by using synthesizable standard cells for control logic (ensuring portability) and custom-optimized circuits for the I/O path (ensuring timing precision). This segmentation allows standard cell libraries to provide foundry portability while hand-designed buffers deliver the timing precision needed for high frequencies.
Solution Approach 2:
The synthesized control logic acts as an intermediary between the portable standard cell domain and the high-performance custom I/O buffer domain. It generates control signals that coordinate the operation of both regions, allowing the system to benefit from both standard cell portability and custom circuit precision.
3Productivity
If manual intervention is applied to optimize timing, then high data rates can be achieved, but implementation complexity and testing difficulty increase
Solution Approach 1:
Manual timing optimization is applied only to the I/O buffer portion of the interface, while the control logic remains fully synthesized with standard tools. This segmentation limits the complexity of hand-designed circuits to only where necessary for achieving high data rates, keeping the rest of the system simple and automatically designable.
4Productivity
If manual intervention is applied to optimize timing, then high data rates can be achieved, but testing and verification effort increases
Solution Approach 1:
The interface is segmented into synthesizable control logic and custom I/O buffers, allowing automated synthesis tools to handle the majority of the design and generate readable, verifiable code. Only the critical I/O portion requires manual optimization and additional testing, reducing overall verification effort compared to fully manual design.
Data Source
AI summary
In a memory interface, a delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow. Physical design of the solidified drive and receive logic blocks permits simple fit within ASIC place and route flows for increased ease of implementation and ease of reuse.