DLL Mode Control Using Clock and Voltage Detection
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Solution Overview
Problem
Existing DLL circuit control methods face challenges in reducing power consumption while maintaining operational efficiency, particularly in display driver ICs, as they require external signals for mode switching, leading to increased costs and potential power wastage due to improper timing and unstable operation during frequency transitions.
Innovation Solution
A DLL operation mode control circuit that compares clock frequencies and common terminal voltages to generate a standby enable signal, allowing automatic switching between normal and standby modes without external input, thereby minimizing power consumption and preventing malfunctioning intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the DLL circuit is driven to increase clock frequency, then operation speed of the IC is improved, but power consumption increases
Solution Approach 1:
The DLL circuit dynamically switches between normal operation mode and standby mode based on real-time detection of operational status and clock frequency, allowing the system to adapt power consumption levels to actual performance requirements rather than operating at fixed high power levels
Solution Approach 2:
The system changes operational parameters by detecting clock frequency thresholds and automatically transitioning the DLL circuit between different operational states (normal and standby), thereby adjusting power consumption parameters according to actual speed requirements
2Adaptability or versatility
If an external standby enable signal pin is added to control DLL mode switching, then mode switching capability is improved, but device complexity and cost increase
Solution Approach 1:
The DLL circuit performs self-diagnosis and automatic mode switching by internally detecting operational status and clock frequency, eliminating the need for external control pins and manual intervention, thereby reducing device complexity while maintaining adaptability
Solution Approach 2:
The system implements automatic feedback control by continuously monitoring operational status and clock frequency, then automatically adjusting the DLL mode accordingly, removing the need for external signal pins and reducing overall system complexity
3Ease of operation
If automatic mode switching is implemented without external signals, then ease of operation is improved, but reliability may worsen due to potential malfunctioning intervals during frequency transitions
Solution Approach 1:
The system performs preliminary detection of operational status and clock frequency before initiating mode transitions, and includes mechanisms to prevent malfunctioning intervals during frequency transitions, ensuring reliable automatic switching without external signals
Data Source
AI summary
A delay-locked loop (DLL) operation mode control circuit and corresponding method are provided in which one of the output values from a display driver IC (DDI) is detected to switch a DLL block to standby mode. In examples, a CLKP/N frequency and CLKP/N common terminal voltage status are used to switch mode. Accordingly, since inoperable frequency domains otherwise present in a normal mode interval of the DLL block is included into standby mode, more stable operation of the DLL circuit is provided.