DLL Delay Chain with Multiple Paths for Wide-Range Phase Shifts
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Solution Overview
Problem
Existing delay-locked loop (DLL) circuits face challenges in achieving a required phase shift over a wide frequency range, particularly for higher frequency data and clock signals, due to limitations in the number of delay circuits, which results in duty cycle distortion and reduced phase options, making it difficult to support features like DDR3 memory applications.
Innovation Solution
A DLL circuit with 8 delay circuit elements in a series, each having the same delay architecture and size transistors, forms a digitally controlled delay chain that adjusts delays based on Gray coded count signals to generate multiple phase offsets, allowing for flexible routing through variable and fixed delay paths to support a wide frequency range without the need for frequency overlap across PVT corners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of delay circuits is increased to achieve required phase shift over wide frequency range, then phase options are improved, but duty cycle distortion increases and device complexity increases
Solution Approach 1:
The delay circuit is divided into multiple delay elements (first delay element, second delay element, third delay element) that can be independently controlled. Each delay element provides a specific delay amount, and by selectively enabling different combinations of these elements, the circuit achieves multiple phase options without requiring a proportional increase in the total number of delay circuits. This segmentation allows efficient utilization of each delay element's contribution to the overall phase shift capability.
Solution Approach 2:
The delay circuit employs dynamic control mechanisms where delay elements can be selectively enabled or disabled based on the required phase shift. The circuit transitions from a static configuration to a dynamic one where the effective number of active delay elements varies with operating conditions, allowing the same physical hardware to provide different phase options by changing which delay elements are active rather than requiring all possible delay paths to be physically present simultaneously.
2Adaptability or versatility
If the number of delay circuits is increased to support higher frequency applications, then frequency range is improved, but duty cycle distortion increases
Solution Approach 1:
The delay circuit is segmented into multiple independently controllable delay elements, each contributing a specific delay amount. This segmentation allows the circuit to achieve the required total delay for higher frequency applications by activating only the necessary number and combination of delay elements, rather than passing the signal through a long chain of many delay circuits. This reduces the cumulative duty cycle distortion that would otherwise accumulate across numerous sequential delay stages.
3Adaptability or versatility
If delay circuits are coupled in series to increase total delay, then phase shift capability is improved, but the number of delay circuits increases
Solution Approach 1:
The total delay requirement is segmented into discrete delay elements with specific delay amounts. Instead of using a single long series chain of many small delay circuits, the invention uses a segmented architecture where fewer, larger delay elements are selectively activated. This segmentation reduces the total number of delay circuits needed while maintaining the same phase shift capability, as each delay element can provide a substantial portion of the required total delay.
Data Source
AI summary
A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits includes variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit.