Delay-Locked Loop Noise Control for Fast Clock Relocking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing delay locked loop circuits fail to effectively manage external noise, leading to unintended delay in the internal clock, which causes data output errors in semiconductor memory devices due to accumulated delay in the feedback clock.
Innovation Solution
A delay locked loop circuit with a noise reducing unit that controls the variation of the internal clock's delay amount to be less than a predetermined value, using additional delay units and a noise controller to rapidly relock the internal clock when external noise disappears, thereby minimizing skew between external and internal clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external noise is continuously inputted to the delay locked loop circuit, then the feedback clock delay amount is accumulated, but the internal clock cannot be rapidly relocked after noise removal
Solution Approach 1:
The patent creates a copied version of the feedback clock path by introducing a second feedback clock that bypasses the delay unit. This copy allows the phase comparator to continue operating with accurate phase information even when the original feedback clock is corrupted by noise, enabling rapid detection and correction without waiting for noise removal
Solution Approach 2:
The noise reducing unit acts as an intermediary between the delay unit and the phase comparator. It monitors the phase difference and controls the delay unit to limit delay amount variation, preventing noise accumulation from completely disrupting the locking mechanism and enabling faster recovery
2Reliability
If the delay amount variation is strictly controlled to be less than a predetermined value, then external noise characteristics are improved, but the circuit complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where the phase comparator continuously monitors the phase difference between the reference clock and feedback clock, and the noise reducing unit uses this information to control the delay unit. This closed-loop feedback automatically limits delay amount variation without requiring complex external control circuits
Solution Approach 2:
The noise reducing unit performs multiple functions: it limits delay amount variation, prevents noise accumulation, and enables rapid relocking. By consolidating these functions into a single control unit that leverages existing phase comparator output, the patent avoids the need for separate complex circuits for each function
Data Source
AI summary
A delay locked loop circuit includes a delay locking unit configured to output an internal clock by delaying a reference clock as much as a first delay amount in response to a phase comparison result of comparing a phase of the reference clock with a phase of a feedback clock that is generated based on delay modeling of a semiconductor memory device, and a noise sensor configured to control variation of the first delay amount caused by an external noise to be less than a second delay amount after locking the internal clock.