Delay-Locked Loop Offset Cancellation Under PVT Variations
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Solution Overview
Problem
Existing delay locked loops face synchronization issues due to process voltage temperature (PVT) variations, leading to clock skew and offset between internal circuits and replica circuits, which prevents accurate synchronization with external clocks in electronic devices.
Innovation Solution
A delay locked loop design incorporating first, second, and third delay circuits, phase detectors, and controllers to detect and adjust delays, ensuring synchronization by replicating clock paths and maintaining constant phase differences across reference, second, and third clocks, thereby compensating for PVT-induced variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If replica circuits are used to synchronize internal circuits with external clocks, then clock skew compensation is achieved, but process voltage temperature (PVT) variations cause differences between internal and replica circuits leading to synchronization failure
Solution Approach 1:
The patent uses replica circuits that copy the structure and characteristics of internal circuits to model their behavior under PVT variations. By replicating the clock path and circuit characteristics, the system can measure and compensate for delays caused by PVT variations, maintaining synchronization accuracy despite environmental changes.
Solution Approach 2:
The patent implements a feedback mechanism where phase detectors continuously monitor the phase difference between internal and replica clock signals. Based on this feedback, delay elements dynamically adjust their delay amounts to compensate for PVT variations, ensuring that the internal circuits remain synchronized with external clocks despite changing conditions.
2Reliability
If delay locked loop adjusts delay to compensate clock skew, then synchronization is improved, but offset between internal and replica circuits persists due to PVT variations
Solution Approach 1:
The patent creates accurate copies of internal circuits as replica circuits, ensuring that the replica circuits experience the same PVT variations as the internal circuits. This copying approach allows the phase detector to accurately measure the actual delay differences caused by PVT variations, improving measurement precision.
Solution Approach 2:
The patent introduces replica circuits as an intermediary between internal circuits and the phase detector. The replica circuits act as a mediator that experiences the same PVT variations as internal circuits but provides a measurable reference signal, enabling accurate phase detection and offset compensation without directly measuring internal circuit delays.
3Device complexity
If single phase detector is used to detect phase difference, then circuit complexity is reduced, but offset cancellation between internal and replica circuits is insufficient
Solution Approach 1:
The patent divides the phase detection function into two separate phase detectors, each responsible for detecting phase differences at different stages of the clock path. This segmentation allows independent optimization of each detector's function and enables more comprehensive offset cancellation by addressing different sources of phase errors separately.
Solution Approach 2:
The patent applies different phase detection and compensation strategies to different parts of the clock distribution network. By using multiple phase detectors positioned at different locations, the system can locally compensate for PVT variations specific to each region, improving overall offset cancellation while maintaining manageable circuit complexity.
Data Source
AI summary
A delay locked loop according to some example embodiments of the inventive concepts may include first, second, and third delay circuits, first and second phase detectors, and first and second controllers. The first delay circuit may generate a first clock by delaying a reference clock. The second and third delay circuits may be configured to generate a second and third clock respectively by delaying the first clock. The first and second phase detector may be configured to detect a phase difference between the second clock and the third clock and the third clock respectively. The first controller may be configured to adjust a delay of the third delay circuit using a detection result of the first phase detector. The second controller may be configured to adjust a delay of the first delay circuit using a detection result of the second phase detector.