DLL Operation Mode Setting Apparatus for Clock Phase Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor integrated circuits lack adaptability to errors caused by external jitter and variations in PVT (process, voltage, and temperature), limiting their ability to reset the DLL circuit and maintain accurate data output due to the fixed nature of the locking completion signal.
Innovation Solution
An operation mode setting apparatus that generates a locking suspension signal to enable re-initialization of the locking completion signal, allowing the DLL circuit to switch between coarse and fine locking modes based on phase differences, thereby adapting to clock state variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the locking completion signal is initialized only at the initial stage, then the operation mode setting apparatus can be simplified, but the adaptability to clock state variations deteriorates
Solution Approach 1:
The locking completion signal is transformed from a static initialization-only signal to a dynamic signal that can be re-initialized during operation. The phase comparison signal, generated by continuously comparing reference clock and feedback clock phases, triggers re-initialization of the locking completion signal when phase differences exceed a threshold, enabling the system to adapt to clock state variations such as external jitter and PVT variations.
2Device complexity
If only fine locking mode is used after initial coarse locking, then the device complexity is reduced, but the correction speed of clock phase errors deteriorates
Solution Approach 1:
The system implements periodic switching between coarse locking mode and fine locking mode based on phase comparison results. When the phase comparison signal indicates a large phase difference, the system switches to coarse locking mode for rapid correction. When the phase difference is small, it switches to fine locking mode for precise adjustment. This periodic mode switching enables both fast correction and high precision.
3Device complexity
If the locking completion signal level is maintained after initialization, then the latch circuit operation is simplified, but the ability to reset DLL circuit deteriorates
Solution Approach 1:
A feedback mechanism is introduced where the phase comparison signal, generated by continuously monitoring the phase difference between reference clock and feedback clock, controls the re-initialization of the locking completion signal. When the phase comparison signal indicates that the phase difference exceeds a threshold, it triggers the re-initialization of the locking completion signal, enabling the DLL circuit to reset and switch to coarse locking mode for error correction.
Data Source
AI summary
An operation mode setting apparatus includes an operation mode setting control unit that discriminates the phase of a reference clock from the phase of a feedback clock and generates a locking suspension signal, and an operation mode setting unit that generates a locking completion signal in response to a pulse signal and a phase comparison signal under the control of a reset signal and the locking suspension signal.