Memory DLL Output Enable Timing for Variable CAS Latency
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Solution Overview
Problem
Conventional semiconductor memory devices require designers to predict and set the total delay time of the delay locked loop (DLL) to select the appropriate output enable signal based on CAS latency, which is time-consuming and inflexible.
Innovation Solution
A semiconductor memory device with a DLL that generates a select signal based on CAS latency and total delay time, allowing flexible selection of output enable signals without additional settings, using a delay locked loop, latch units, a delay unit, a counting unit, a select signal generating unit, and an output enable signal generating unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If designers manually predict and set the total delay time of the DLL to select the appropriate output enable signal, then the device can operate correctly, but the design process becomes time-consuming and inflexible
Solution Approach 1:
The output enable signal generating unit automatically measures the total delay time of the DLL and selects the appropriate output enable signal based on the measured value and CAS latency, eliminating the need for manual designer prediction and setting. The device performs self-testing and self-configuration, making the design process faster and more flexible while ensuring correct operation.
2Device complexity
If the output enable signal is fixed based on predicted delay time, then the device structure is simple, but it cannot adapt to different CAS latency values and external clock characteristics
Solution Approach 1:
The output enable signal generating unit dynamically adjusts the selection of output enable signals based on real-time measurements of the DLL's total delay time and the required CAS latency. Instead of using a fixed signal, the system continuously adapts by measuring the actual delay and selecting the appropriate signal from multiple options, enabling flexibility across different operating conditions while maintaining a manageable structure through automated control logic.
Data Source
AI summary
A semiconductor memory device includes: a delay locked loop (DLL) for delaying an external clock to generate a DLL clock; an output control unit for generating a select signal based on a column address strobe (CAS) latency signal and a delay time corresponding to a total delay time of the DLL being in a delay locked state; and an output enable signal generating unit for generating a plurality of output enable signals in response to the DLL clock and outputting a final output enable signal in response to the select signal.