Delay Locked Loop Periodic Locking Power Down
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Solution Overview
Problem
Semiconductor devices with Delay Locked Loops (DLLs) face increased power consumption due to large current usage in locking operations, leading to prolonged locking times and decreased operational speed when entering power down mode, as disabling the DLL during power down mode results in increased phase differences between external and internal clock signals upon resuming active mode.
Innovation Solution
A DLL design that periodically enables the locking operation during power down mode using a power down control unit to manage global clock signals, phase detection, and delay units, allowing for reduced power consumption and faster locking times upon resuming active mode by minimizing phase differences between external and internal clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the DLL is disabled during power down mode to decrease power consumption, then power consumption decreases, but locking operation time increases after resuming active mode
Solution Approach 1:
The DLL is enabled periodically during power down mode to perform locking operations at predetermined intervals. The power down control unit receives global clock signals and periodically enables the DLL to execute locking operations, then disables it again to maintain low power consumption. This periodic enabling maintains clock signal synchronization while minimizing power usage.
2Speed
If the DLL is continuously enabled to maintain fast operational speed, then locking operation time decreases, but power consumption increases
Solution Approach 1:
Instead of continuous operation, the DLL performs locking operations periodically during power down mode. The power down control unit enables the DLL at predetermined intervals based on global clock signals, allowing the system to maintain adequate synchronization while consuming significantly less power compared to continuous operation.
3Use of energy by moving object
If the DLL is disabled for extended periods in power down mode, then power consumption decreases, but phase difference between clock signals increases
Solution Approach 1:
The DLL is enabled periodically during power down mode to perform locking operations that maintain phase synchronization between the internal clock signal and external clock signal. This periodic operation prevents excessive phase accumulation while keeping the DLL disabled most of the time to save power.
Solution Approach 2:
The phase detection unit continuously monitors the phase difference between clock signals and provides feedback to the delay control unit. This feedback mechanism allows the DLL to correct phase deviations when enabled, ensuring synchronization is maintained despite periodic enabling/disabling operations.
Data Source
AI summary
A Delay Locked Loop (DLL) having a function of periodically executing a locking operation during a power down mode and a locking operation method of the same, which includes a global clock generator, a clock delay unit, and a power down control unit. The power down control unit, in response to some of a plurality of global clock signals, a phase detection signal, and a power down signal, outputs an input clock signal to each of the global clock generator and the clock delay unit. During the power down mode, the clock delay unit is enabled to periodically carry out the locking operation whenever it receives the input clock signal. Therefore, a consumed power of the DLL can be decreased during the power down mode, and a phase difference between an external clock signal and an internal clock signal during the power down mode can be decreased by the periodical locking operation of the clock delay unit, so that the DLL can operate at a fast speed after the power down mode.