Digital Delay Lock Loop Using Phase Accumulation for Clock Alignment
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Solution Overview
Problem
Conventional delay lock loop (DLL) circuits in digital systems are susceptible to unwanted latencies due to characteristics of analog circuitry, particularly at higher frequencies and with smaller feature sizes, leading to inaccuracies and reliability issues.
Innovation Solution
The implementation of digitally controlled DLL circuits that combine digital and analog components to mitigate errors and improve accuracy, using a phase detector, phase accumulator, decoder, and delay element to align clock signals, enabling fine and coarse tuning modes for precise phase alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional analog delay lock loop circuits are used, then the circuit can operate at basic frequencies, but unwanted latencies and errors occur at higher frequencies and smaller feature sizes
Solution Approach 1:
The patent replaces the analog delay element with a digitally controlled delay line that uses digital logic circuits (D-flip flops, multiplexers, and counters) to achieve precise delay control. This substitution eliminates the inherent latencies and errors of analog circuitry while maintaining the delay lock loop's core functionality of aligning clock signals at high frequencies
Solution Approach 2:
The patent changes the control parameter from analog voltage to digital control words that selectively enable/disable delay stages. The delay amount is controlled by a digital counter value that can be precisely adjusted, allowing accurate phase alignment without the latencies associated with analog parameter changes
2Measurement precision
If digitally controlled DLL circuits are implemented, then latency is reduced and accuracy is enhanced, but device complexity increases due to additional digital components
Solution Approach 1:
The delay line is segmented into multiple discrete delay stages, each controlled by individual enable signals from a decoder. This segmentation allows precise control of the total delay amount by selectively activating specific stages, achieving high measurement precision while keeping each individual stage simple and manageable
Solution Approach 2:
The digital control circuitry serves multiple functions: it controls the delay amount, generates enable signals for the delay stages, and can be programmed to achieve different phase alignments. This multi-functionality reduces the need for separate control circuits, thereby managing device complexity while enhancing phase alignment accuracy
Data Source
AI summary
Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.