Digital Delay Lock Loop Circuit With Phase Accumulation Control
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Solution Overview
Problem
Conventional delay lock loop (DLL) circuits in digital systems are susceptible to unwanted latencies due to characteristics of analog circuitry, particularly at higher frequencies and with smaller feature sizes, leading to inaccuracies and reliability issues.
Innovation Solution
The implementation of digitally controlled DLL circuits that utilize a phase detector, phase accumulator, decoder, and delay element to align clock signals, combining digital and analog circuitry to mitigate latency and improve accuracy and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional analog delay lock loop circuits are used, then the circuit can operate at basic frequencies, but unwanted latencies and inaccuracies occur at higher frequencies and smaller feature sizes
Solution Approach 1:
The patent replaces the conventional analog delay lock loop circuit with a digitally controlled delay lock loop circuit. The digital circuit uses a phase detector, digital counter, and digital delay elements instead of analog components, thereby eliminating the unwanted latencies and inaccuracies that plague analog implementations at high frequencies and small feature sizes.
Solution Approach 2:
The patent changes the operating parameters by using digital control signals to adjust delay elements. The digital counter accumulates phase difference information and generates control words that precisely adjust the delay amount, allowing accurate phase alignment across a wide frequency range without the latencies inherent in analog systems.
2Reliability
If digitally controlled DLL circuits are implemented, then accuracy and reliability are improved, but device complexity increases
Solution Approach 1:
The digital delay lock loop circuit is segmented into distinct functional blocks: a phase detector for measuring phase differences, a digital counter for accumulating phase information over multiple clock cycles, a digital delay line with controllable delay elements, and a control logic unit. This modular segmentation makes the complex digital circuit more manageable and implementable while maintaining high accuracy.
Data Source
AI summary
Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.