Synchronous Data System Phase-Aligned Output Using DLLs
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Solution Overview
Problem
Conventional synchronous digital systems face challenges in generating phase-aligned data due to clock signal synchronization issues, such as jitter and noise performance, and reliance on a single master device, which affects reliability.
Innovation Solution
A synchronous data system utilizing multiple transmitter-receiver pairs with delay-locked loops (DLLs) that include adjustable phase shifters to synchronize module clocks with a system clock, minimizing phase errors and achieving edge-alignment of high-speed clocks, along with frequency multipliers and dividers to generate phase-aligned output data without relying on a single master device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase-locked loops with voltage-controlled oscillators are used to generate synchronous data, then clock synchronization is achieved, but jitter and noise performance deteriorate
Solution Approach 1:
The patent extracts and eliminates the voltage-controlled oscillator from the synchronization system, replacing it with a delay-locked loop that uses fixed-frequency clocks and programmable delay elements. This removal of the VCO component directly resolves the jitter and noise performance issues while maintaining clock synchronization capability.
Solution Approach 2:
The patent substitutes the analog voltage-controlled oscillator mechanism with a digital delay-locked loop mechanism using programmable delay elements and fixed-frequency clocks. This mechanical/electrical substitution eliminates the inherent instability of VCOs while achieving the same synchronization function.
2Device complexity
If a single master device is used in a master-slave approach to generate synchronous data, then system complexity is reduced, but reliability deteriorates due to single point of failure
Solution Approach 1:
The patent segments the synchronization function by distributing delay-locked loop circuits to each slave device, allowing each device to independently synchronize with the master clock. This segmentation eliminates the single point of failure while maintaining relatively simple system architecture through standardized DLL modules.
Solution Approach 2:
The patent introduces delay-locked loop circuits as intermediary synchronization mechanisms between the master clock and slave devices. These DLLs act as local synchronization intermediaries that eliminate the direct dependency on the master device while maintaining system-wide synchronization.
3Device complexity
If conventional clock distribution methods are used across the system, then system simplicity is maintained, but phase alignment deteriorates due to propagation delays and clock buffer delays
Solution Approach 1:
The patent introduces programmable delay elements that can dynamically adjust their delay characteristics to compensate for varying propagation delays in different clock distribution paths. This dynamic adjustment capability enables precise phase alignment while maintaining a relatively simple clock distribution architecture.
Solution Approach 2:
The patent implements delay-locked loop feedback mechanisms that continuously monitor and adjust clock phase alignment. The feedback control enables automatic compensation for propagation delays and buffer delays, achieving precise phase alignment without requiring complex pre-calibrated clock distribution systems.
Data Source
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AI summary
Embodiments of a synchronous data system and method for generating phase-aligned output data are generally described herein. In some embodiments, the synchronous data system includes a plurality of transmitter-receiver (TX-RX) pairs, each associated with a delay-locked loop (DLL) and arranged to generate corresponding output data stream based on a high-speed clock of the associated TX-RX pair. The DLL associated with each TX-RX pair is a phase-shifter DLL that includes an adjustable phase shifter arranged to minimize the phase error between the system clock and the module clock to edge-align the high-speed clocks of each TX-RX pair.