Delay Locked Loop Phase Blending for Low Bang-Bang Jitter
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Solution Overview
Problem
Conventional delay locked loops experience increased bang-bang jitter when phase-blending delayed signals near the edge of the delayed signals, which affects data synchronization in high bus load and high transmission frequency systems.
Innovation Solution
Incorporating an auxiliary phase shifter that controls the phase blending point by delaying the clock signal by a predefined time, θ/2, to phase-blend signals between the edges rather than near them, thereby reducing jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If phase blending is performed near the edge of delayed signals in a conventional delay locked loop, then the phase error can be reduced, but bang-bang jitter increases
Solution Approach 1:
The auxiliary phase shifter performs preliminary phase shifting of the clock signal by a predefined time (θ/2) before the phase blending operation. This preliminary action positions the phase blending point between the edges of delayed signals rather than near them, thereby reducing bang-bang jitter while maintaining phase error correction capability
Solution Approach 2:
The auxiliary phase shifter acts as an intermediary component that modifies the clock signal phase before it enters the phase blending stage. By introducing this intermediate phase shift, the system avoids direct phase blending near signal edges, thus reducing jitter while still achieving phase synchronization
Data Source
AI summary
A delay locked loop includes an auxiliary phase shifter for controlling a phase blending point after the delay locked loop is initially locked, thereby reducing jitter. A control circuit directs a phase blender to detect the point where two delayed signals are phase-blended, and directs the auxiliary phase shifter to select between a delayed clock signal and a received clock signal. When the point where the two delayed signals are phase-blended is in-between first edges of the two delayed signals, the control circuit directs the auxiliary phase shifter to transmit the received clock signal without delaying the clock signal. When the point where the two delayed signals are phase-blended is close to at least one of the first edges of the two delayed signals, the control circuit directs the auxiliary phase shifter to delay the clock signal by a predefined time. As a result, bang-bang jitter in the delay locked loop is reduced.