DLL Data Reception with Phase Detection for DDR Latching
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Solution Overview
Problem
Current semiconductor apparatuses face challenges in accurately latching external data at high speeds, particularly with DDR schemes, where data must be synchronized at both rising and falling edges of the clock signal, requiring precise phase control of the data latch clock signal to ensure proper data alignment and operation.
Innovation Solution
A semiconductor apparatus incorporating a clock receiving unit, a delay locked loop (DLL) to generate a data latch clock signal with variable delay, a data receiving unit for synchronized data reception, and a determination unit to detect phase differences between the reference and data latch clock signals, along with a data sorting unit to differentiate data based on the DLL locking signal, ensuring accurate data alignment and sorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DDR scheme is used to improve operation speed, then data reception speed is improved, but phase control precision requirement increases
Solution Approach 1:
The patent changes the phase parameter of the data latch clock signal by using a DLL circuit to generate multiple phase-shifted clock signals (e.g., 0°, 90°, 180°, 270° phases). This allows the system to operate at high DDR speeds while maintaining precise phase control through programmable phase selection, resolving the contradiction between high speed and precision requirements.
Solution Approach 2:
The patent implements dynamic phase adjustment by allowing the system to selectively switch between different phase-shifted clock signals based on data alignment requirements. The determination unit dynamically identifies the correct phase relationship between reference clock and data latch clock, enabling adaptive phase control that maintains precision across varying operational conditions.
2Measurement precision
If phase of data latch clock signal is controlled to accurately latch data, then data latching accuracy is improved, but device complexity increases
Solution Approach 1:
The patent employs a feedback mechanism where the determination unit detects the phase relationship between the reference clock signal and the data latch clock signal, generates a determination signal, and feeds this information back to the data sorting unit. This feedback loop automatically adjusts data sorting based on actual phase conditions, achieving accurate data latching without requiring complex manual phase control circuits.
Solution Approach 2:
The system performs self-adjustment by using the determination unit to automatically identify and signal the correct phase alignment between clocks. The data sorting unit then autonomously sorts internal data based on the determination signal, eliminating the need for external intervention or complex control logic, thereby reducing overall device complexity while maintaining high latching accuracy.
3Manufacturing precision
If internal data are sorted based on rising and falling edges, then data alignment is improved, but additional circuitry is required
Solution Approach 1:
The determination unit serves multiple functions: it detects phase differences, determines the relationship between reference and latch clocks, generates determination signals, and enables both rising-edge and falling-edge data sorting. This multi-functional component achieves precise data alignment without requiring separate dedicated circuits for each sorting function, thereby minimizing additional circuitry while improving data alignment capability.
Data Source
AI summary
A semiconductor apparatus includes: a clock receiving unit configured to receive an external clock signal and output the received clock signal as a reference clock signal; a delay locked loop (DLL) configured to delay the reference clock signal by a variable delay amount and generate a data latch clock signal; a data receiving unit configured to receive external data in synchronization with the data latch clock signal and output the received data as internal data; and a determination unit configured to detect a phase difference between the reference clock signal and the data latch clock signal and generate a determination signal, when the DLL is locked.