DLL Phase Synchronization Using Multi-Sample Delay Adjustment
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Solution Overview
Problem
DLL and PLL circuits in electronic devices face challenges in maintaining synchronization due to jitter and noise, which affects the phase relationship between generated and reference signals, particularly in high-speed applications like SDRAM devices.
Innovation Solution
The proposed solution involves a DLL circuit with a phase detection interface, coarse and fine variable delay lines, and a high-speed multi-measure logic circuit that calculates and adjusts the phase difference between reference and feedback signals to maintain synchronization, using a combination of digital signal processing and analog circuits to generate a feedback signal that aligns with the reference signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DLL or PLL circuits are used to generate periodic signals, then clock signal generation is achieved, but synchronization is compromised due to jitter and noise
Solution Approach 1:
The patent implements a feedback mechanism where the generated clock signal is fed back to the phase detector, which continuously compares it with the reference signal and adjusts the delay elements to maintain synchronization despite jitter and noise interference
Solution Approach 2:
The patent introduces delay elements as intermediary components between the reference signal and the output clock signal. These delay elements act as mediators that can be dynamically adjusted to compensate for phase deviations caused by jitter and noise, thereby maintaining synchronization
2Reliability
If phase adjustment is performed to maintain synchronization, then synchronization is improved, but circuit complexity increases
Solution Approach 1:
The patent segments the phase adjustment function into multiple independent delay elements that can be individually controlled. This segmentation allows for finer granularity in phase adjustment and simplifies the control logic by breaking down the complex synchronization task into manageable discrete steps
Solution Approach 2:
The patent employs dynamically adjustable delay elements whose delay characteristics can be changed in real-time based on the phase error detected by the phase detector. This dynamic adjustment capability allows the circuit to adapt to varying synchronization requirements without requiring a completely complex redesign
Data Source
AI summary
Apparatus, systems, and methods are disclosed that operate to generate a periodic output signal from a periodic input signal, obtain a plurality of samples of a phase difference between the output signal and the input signal, and to adjust a phase of the output signal based on the samples of the phase difference. Additional apparatus, systems, and methods are disclosed.