Delay-Locked Loop Phase Detector for Low-Power Phase Shifting
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Solution Overview
Problem
Existing delay-locked loops (DLLs) face challenges in reducing power consumption while maintaining precise phase shifting, especially as clock frequencies increase, and often rely on master Phase-Locked Loops (PLLs) for phase and frequency information, which can lead to inefficiencies.
Innovation Solution
A DLL design that includes a voltage-controlled delay line, a phase detector generating charge up and charge down control signals based on phase differences, and a charge pump with switching transistors controlled by these signals to manage current flow efficiently, allowing for reduced power consumption and fine-tuned phase shifting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a DLL uses a voltage-controlled delay line and phase detector to achieve precise phase shifting, then phase shifting accuracy is improved, but power consumption increases
Solution Approach 1:
The charge pump operates periodically based on phase detection results rather than continuously. The phase detector generates periodic control signals that activate the charge pump only when phase adjustment is needed, reducing overall power consumption while maintaining precise phase shifting capability when required
Solution Approach 2:
The system dynamically adjusts the control voltage applied to the voltage-controlled delay line based on detected phase differences. By changing the voltage parameter in response to actual phase error, the system achieves precise phase shifting only when needed rather than maintaining constant high-power operation
2Productivity
If a DLL operates independently without relying on master PLL, then system efficiency is improved, but the complexity of generating reference clock signals increases
Solution Approach 1:
The DLL circuit is designed to generate its own reference clock signals using an internal clock signal and phase detection mechanism. The phase detector compares the delayed clock signal with the reference and automatically adjusts the delay line, enabling the DLL to operate independently without external master PLL control while maintaining system efficiency
Solution Approach 2:
The patent combines the reference clock generation function with the delay-locked loop operation. The internal clock signal is directly used as reference by the phase detector, merging multiple functions into a single integrated circuit that achieves both independence and efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables DLLs with reduced power consumption and improved phase shifting accuracy, eliminating the need for additional reference clock signals and allowing for independent operation, thus enhancing overall system efficiency.
Implementation Method 1
a voltage control delay line for receiving a reference clock signal and for delaying the reference clock signal to provide a feedback clock signal
Implementation Method 2
A phase detector receives the reference clock signal, an additional reference signal, and the feedback clock signal. The phase detector generates charge up and charge down control signals dependent upon a phase difference between the reference clock signal and the feedback clock signal
Implementation Method 3
A charge pump includes at least two switching transistors. One of the switching transistors permits current to be added into the capacitor when switched on in response to the charge up signal. Another of the switching transistors permits current to be removed from the capacitor when switched on in response to the charge down signal
Data Source
AI summary
The disclosure relates to phase detectors. Charge up and charge down signals that are generated by a phase detector cause i) following detection of a first edge of a reference clock signal, switching on of a switching transistor of sink current; ii) following detection of an edge of a feedback clock signal falling within less than 180 degrees from the first edge, switching on of a switching transistor of source current and switching off of the switching transistor of sink current; and iii) following detection of an edge of another reference signal at a point in time about midway between the first edge and a next similar edge of the reference clock signal has past, switching off of the switching transistor of source current while maintaining the switching transistor of sink current switched off.