DLL Phase Detector Circuit for 270° and 540° Clock Shift Detection
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Solution Overview
Problem
Conventional phase detectors are inadequate for detecting phase differences greater than 90 or 180 degrees, particularly 270 and 540 degrees, which is essential for high-speed clock signals in modern digital circuits, as they struggle to accommodate timing variations due to PVT effects.
Innovation Solution
A phase detector system for delay-locked loops (DLLs) that generates and detects 270 and 540 degree phase shifts, utilizing a charge pump and regulator circuit to control the delay chain, ensuring accurate phase detection and adjustment across a wider range of timing variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional phase detectors are used to detect 90 or 180 degree phase differences, then the detection is accurate within limited range, but the detector cannot detect 270 or 540 degree phase differences required for high-speed clock signals
Solution Approach 1:
The phase detector is divided into multiple detection paths: a first phase detector for detecting 90-degree phase differences and a second phase detector for detecting 180-degree phase differences. These segmented detectors work together with a selection mechanism to achieve comprehensive detection of 270 and 540 degree phase shifts, resolving the limitation of conventional single-range detectors.
2Stability of the object's composition
If the delay chain accommodates more delay elements to cover PVT variations, then the constant delay is maintained across conditions, but the total delay exceeds 90 degrees and cannot be detected by conventional phase detectors
Solution Approach 1:
The system dynamically switches between different phase detection modes based on the required delay range. A selection circuit chooses between the first phase detector (for 90-degree detection) and the second phase detector (for 180-degree detection) depending on the operating conditions and delay requirements, enabling the system to adaptively handle both small and large phase shifts while maintaining detection accuracy.
3Productivity
If clock speed is increased to 5 GHz for high-speed applications, then the productivity is improved, but the clock period decreases making it difficult to accommodate all delay elements within 90 degrees
Solution Approach 1:
The system changes the detection parameter from fixed 90-degree phase difference detection to variable detection ranges (90 or 180 degrees) based on operating conditions. This parameter change allows the phase detector to work effectively with shorter clock periods at high speeds by selecting the appropriate detection range that matches the available time window within each clock cycle.
Data Source
AI summary
Embodiments include implementing a phase detector for a delay-locked loop (DLL) circuit that is operable to detect substantially 270 degree and substantially 540 degree phase differences between two clock signals. In an embodiment, a DLL circuit comprises a delay line receiving a system clock signal and generating a substantially 270 degree phase shifted clock signal and a substantially 540 degree phase shifted clock signal, a phase detector receiving the system clock signal and the substantially 270 degree phase shifted clock signal, and configured to generate corresponding up and down signals upon detection of a phase shift of substantially 270 degrees between the system clock signal and the substantially 270 degree phase shifted clock signal, a charge pump coupled to the phase detector, and configured to receive the up and down signals and generate a control signal responsive to thereto, and a regulator circuit to receive the control signal from the charge pump and generate a voltage control signal to the delay chain to control delay of the system clock signal.