Digital Frequency Synthesizer Using DLL Phase Selection for Fractional Clocks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional digital frequency synthesizers are unable to meet the clock frequency requirements of functional circuits that need non-integer-divided versions of the clock frequencies, due to their limited resolution and increased complexity when trying to improve resolution.
Innovation Solution
The digital frequency synthesizer employs a combination of two delay-locked loops (DLLs), two output delay chains, and four clock selectors to generate fractional-divided clock signals with a duty cycle close to 50%, overcoming the limitations of traditional VCO-based synthesizers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional digital frequency synthesizers use integer division only, then the device complexity remains low, but the measurement precision of clock frequency无法满足非整数倍频需求
Solution Approach 1:
The frequency division is segmented into two independent parts: integer division by divider circuit and fractional division by phase selection circuit. The fractional part is achieved by selecting different phases from multiple delayed clock signals, avoiding the need for complex fractional division logic while achieving precise frequency control.
Solution Approach 2:
The patent transitions from one-dimensional integer division to two-dimensional frequency control by adding phase dimension. Multiple clock signals with different phases are generated through delay elements, and the desired frequency is achieved by selecting appropriate phase combinations, effectively adding a temporal dimension to the frequency synthesis.
2Measurement precision
If VCO-based synthesizers are used to achieve fractional division, then the measurement precision improves, but the device complexity and dynamic power consumption increase
Solution Approach 1:
The patent replaces the VCO (voltage-controlled oscillator) mechanical/electronic system with a purely digital phase selection system. Instead of using a VCO to generate variable frequency signals, the invention uses integer division combined with phase-selective combination of fixed-frequency delayed clocks, eliminating the VCO and its associated complexity while achieving the same fractional division effect.
Solution Approach 2:
Multiple copies of the reference clock signal are generated with different phase delays. These copied and delayed signals are then selectively combined to achieve the desired fractional frequency division, avoiding the need for a single complex VCO system.
3Measurement precision
If the resolution of digital frequency synthesizer is increased, then the measurement precision improves, but the dynamic power consumption increases
Solution Approach 1:
The patent uses periodic delayed clock signals generated by the DLL, where each delay element produces a phase-shifted version of the reference clock. By periodically selecting and combining these pre-generated phase signals, the system achieves high-resolution frequency control without continuously varying signal parameters, reducing dynamic power consumption compared to VCO-based approaches.
Data Source
AI summary
A digital frequency synthesizer includes a delay-locked loop (DLL) that generates time-delayed versions of a reference clock signal, a clock divider that executes an integer-division operation on one delayed clock signal to generate an integer-divided clock signal, and control circuitry that generates fractional data for enabling a fractional division. The digital frequency synthesizer further includes a first clock selector that selects one delayed clock signal as a DLL clock signal based on the fractional data, a delay chain that generates time-delayed versions of the DLL clock signal, and a second clock selector that selects one delayed clock signal as a selected clock signal based on the fractional data. A rising edge of the integer-divided clock signal is adjusted based on the selected clock signal to generate a fractional-divided clock signal that is a fractional-divided version of the reference clock signal.