Delay Locked Loop Phase Detection Using Frequency Doubling

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Solution Overview

Problem

Current methods for testing semiconductor devices, particularly delay locked loops/delay lines, cannot accurately determine if a 90-degree phase shift is present between input and output signals, which is crucial for assessing their normal operation.

Innovation Solution

A phase-detecting method and circuit that combines input and output signals to generate a frequency-doubled signal, compares it with a reference clock, filters any differences, and determines if the result is within an acceptable range to report whether a 90-degree phase shift is present.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional testing methods are used to check clock rate or frequency, then the testing process is simple, but the phase shift measurement capability is lost

Engineering Contradiction:
Improvephase shift measurementVSAvoidtesting circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent combines the input signal and output signal through a frequency-doubling circuit that merges both signals together. This merging process generates a frequency-doubled signal that contains phase information, enabling phase shift measurement without requiring separate complex measurement systems. The combination of input and output signals in one circuit achieves both frequency verification and phase measurement.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a frequency-doubled signal as an intermediary between the input/output signals and the phase measurement process. This intermediary signal serves as a mediator that translates the phase relationship between input and output signals into a measurable form by comparing it with a reference clock signal, thereby enabling precise phase shift detection.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If comprehensive phase testing is implemented, then the measurement precision improves, but the testing time increases

Engineering Contradiction:
Improvephase shift determination accuracyVSAvoidtesting time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs preliminary frequency-doubling of the input and output signals before phase comparison. By pre-processing the signals to double their frequency and create a standardized intermediate signal, the actual phase measurement can be performed quickly and efficiently. This preliminary action prepares the signals in advance, reducing the time required for the critical phase determination step.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If phase shift measurement is added to existing testing, then the measurement precision improves, but the device complexity increases

Engineering Contradiction:
Improvephase shift detection capabilityVSAvoidtesting station complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The frequency-doubling circuit serves multiple functions simultaneously: it combines the input and output signals, generates a frequency-doubled signal for comparison, and enables phase shift measurement. This multi-functional approach allows a single circuit element to perform what would otherwise require multiple separate components, thereby adding phase measurement capability without proportionally increasing overall system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10511313B1Phase-detecting method and circuit for testing a delay locked loop/delay line
Publication Date: 2019.12.17 GOKE TAIWAN RES LAB LTD
  • US10511313B1 patent drawing
  • US10511313B1 patent drawing
  • US10511313B1 patent drawing

AI summary

A phase-detecting method for testing an under-test circuit under control of a testing station includes the steps of receiving input and output signals of the under-test circuit, combining the input and output signals with each other and accordingly generating a frequency-doubled signal, comparing the frequency-doubled signal with a reference clock signal at a same clock rate and accordingly generating a difference signal, filtering the difference signal and accordingly generating a filtered signal, and determining whether the filtered signal is in an acceptable range and accordingly report a result to the testing station.