DLL Timing Adjustment with Input Inversion for Shorter Delay Lines
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Solution Overview
Problem
Traditional delay locked loops (DLLs) in semiconductor devices consume significant power and contribute to clock jitter due to the large size of the delay line, which is exacerbated at lower data rates.
Innovation Solution
Inverting the input signal during the DLL initialization process to minimize the variable delay line length, thereby reducing power consumption without increasing circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a traditional delay line is used to provide variable phase adjustments in the DLL, then the phase adjustment capability is achieved, but power consumption increases significantly
Solution Approach 1:
The delay line is segmented into multiple selectable delay stages, where only the necessary number of stages are activated based on the required phase adjustment. This segmentation allows the system to achieve variable phase adjustment capability while minimizing the number of active delay elements, thereby reducing overall power consumption.
Solution Approach 2:
The delay line configuration is made dynamic through selective activation of different delay stages based on real-time requirements. The system dynamically adjusts which delay stages are enabled, optimizing the balance between phase adjustment capability and power consumption for different operating conditions.
2Adaptability or versatility
If a longer delay line is activated to support lower data rates, then data rate adaptability is improved, but power consumption increases
Solution Approach 1:
The delay line is divided into multiple selectable segments or stages, allowing the system to activate only the necessary number of stages required for the current data rate. At lower data rates, fewer stages are activated compared to traditional designs, achieving data rate adaptability while minimizing power consumption by keeping unnecessary delay stages in a low-power state.
Solution Approach 2:
The system changes the operational parameters of the delay line by dynamically adjusting the number of active delay stages based on the required data rate. This parameter adjustment allows the delay line to adapt to different data rates without always operating at maximum length, thereby reducing power consumption at lower data rates.
3Adaptability or versatility
If a large delay line is used to provide variable phase adjustments, then phase adjustment range is improved, but clock jitter increases
Solution Approach 1:
The delay line is segmented into multiple discrete stages, each contributing a controlled amount of phase delay. By selectively activating only the necessary number of stages required for the current phase adjustment need, the system achieves the required phase adjustment range while minimizing the total number of active delay elements, thereby reducing accumulated clock jitter.
Solution Approach 2:
The system applies partial action by activating only the minimum necessary number of delay stages required for the current phase adjustment requirement, rather than always operating with the full delay line activated. This partial activation reduces the number of active components contributing to jitter while still achieving the necessary phase adjustment range.
Data Source
AI summary
An electronic device including: a variable delay circuit configured to adjust a delay of a variable delay input for generating an output signal; a decision circuit coupled to the variable delay, the decision circuit configured to: generate a start signal for the variable delay circuit to begin measuring a coarse delay, generate a stop signal for the variable delay circuit to stop measuring the coarse delay, and generate an inversion-decision signal based at least in part on measuring the coarse delay; and an input selection circuit coupled to the variable delay circuit and the decision circuit, the input selection circuit configured to control a phase for a clock input based on the inversion-decision signal in generating the variable delay input.