DLL Initialization with Input Inversion for Low-Power Phase Adjustment
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Solution Overview
Problem
Traditional delay locked loops (DLLs) in semiconductor devices consume significant power and contribute to clock jitter due to the large size of the delay line, which is exacerbated at lower data rates.
Innovation Solution
Inverting the input signal during the DLL initialization process instead of delaying it beyond a 180-degree phase shift, allowing for a reduced length of the variable delay line, thereby minimizing power consumption without increasing circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a longer delay line is used in traditional DLL to support lower data rates, then the phase adjustment range is improved, but power consumption increases
Solution Approach 1:
The patent inverts the input signal during DLL initialization instead of delaying it beyond a 180-degree phase shift. This inversion approach allows the delay line to be shortened while still achieving the necessary phase adjustment range, thereby reducing power consumption without sacrificing adaptability.
Solution Approach 2:
The patent changes the operating parameter of the delay line by limiting the phase shift to less than 180 degrees and using signal inversion to achieve the remaining phase adjustment. This parameter change allows for a shorter delay line length while maintaining the required phase adjustment capability across different data rates.
2Adaptability or versatility
If a longer delay line is used in traditional DLL, then the phase adjustment range is improved, but clock jitter increases
Solution Approach 1:
By inverting the input signal instead of using a long delay line to achieve large phase shifts, the patent reduces the delay line length and consequently reduces clock jitter while maintaining the required phase adjustment range through the combination of inversion and limited delay.
3Use of energy by moving object
If the delay line length is reduced to lower power consumption, then power efficiency is improved, but the ability to support lower data rates may be compromised
Solution Approach 1:
The patent uses signal inversion during initialization to achieve the necessary phase adjustment for lower data rates without requiring a long delay line. This allows the delay line to be shortened for lower power consumption while the inversion mechanism ensures that data rate support capability is maintained.
Data Source
AI summary
An electronic device including: a variable delay circuit configured to adjust a delay of a variable delay input for generating an output signal; a decision circuit coupled to the variable delay, the decision circuit configured to: generate a start signal for the variable delay circuit to begin measuring a coarse delay, generate a stop signal for the variable delay circuit to stop measuring the coarse delay, and generate an inversion-decision signal based at least in part on measuring the coarse delay; and an input selection circuit coupled to the variable delay circuit and the decision circuit, the input selection circuit configured to control a phase for a clock input based on the inversion-decision signal in generating the variable delay input.