DLL Phase Lock Detection with Asymmetric Jitter Filtering
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Solution Overview
Problem
Conventional lock detectors in Delay-Locked Loops (DLLs) often produce false alarms due to jitter accumulation and intrinsic static offset, making it difficult to distinguish between actual and false out-of-lock conditions.
Innovation Solution
A phase lock detection circuit with a synchronization circuit, phase detectors, and asymmetrical low-pass filtering to provide a cycle lock signal indicating whether a phase lock exists within a lock window, reducing false alarms by differentiating between lock and out-of-lock conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional lock detector is used in a DLL, then the circuit can detect lock conditions, but it produces false alarms due to jitter and intrinsic static offset
Solution Approach 1:
The lock detection function is segmented into multiple independent phase detectors, each comparing different signal pairs (feedback clock with delayed reference, and reference clock with delayed feedback). This segmentation allows the system to gather multiple independent measurements to distinguish true lock conditions from false alarms caused by jitter or static offset.
Solution Approach 2:
The system uses feedback signals from the DLL circuit and feeds them back to the phase detectors for continuous comparison. The feedback mechanism enables real-time monitoring of phase relationships and allows the lock detector to adapt to changing conditions, improving reliability by confirming lock status through multiple feedback cycles rather than a single measurement.
2Reliability
If jitter accumulation is eliminated by using a DLL instead of a PLL, then jitter performance improves, but the lock detector becomes more susceptible to false alarms
Solution Approach 1:
The system employs asymmetric delay elements with different delay values (first delay element and second delay element) to create asymmetric comparison windows. This asymmetry allows the phase detectors to examine phase relationships from different temporal perspectives, making it possible to distinguish between transient jitter effects and genuine lock loss conditions.
Solution Approach 2:
The system performs more phase comparisons than a conventional single detector would need - using multiple phase detectors to compare multiple signal pairs beyond the minimum required for basic lock detection. This excessive action provides redundant information that helps filter out false alarms while maintaining the jitter-free performance advantage of DLLs.
Data Source
AI summary
Method and apparatus for phase lock detection is described. More particularly, a phase lock detection circuit (20) includes a synchronization circuit (23) coupled to receive a reference signal (31) and configured to provide a derivative signal (32). A phase lock detector (21) is coupled to receive the reference signal (31) and the derivative signal (32) and is configured to provide a cycle lock signal (24) indicating whether a phase lock exists within a lock window (57) for a clock cycle.