Delay-Locked Loop Phase Detection for Half-Phase Lock Prevention
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Solution Overview
Problem
Existing DLL circuits face issues with accurate delay locking detection, leading to potential half phase locking failures and phase locking misses due to power noise and jitter components, resulting in unsynchronized data output.
Innovation Solution
The proposed DLL circuit incorporates a coarse delay line, fine delay line, replica delay unit, phase detection units, and a locking detection unit to accurately compare phases and generate locking signals, preventing erroneous locking detections by using multiple phase detection signals and logic level comparisons to ensure precise synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional locking detector is used to detect delay locking completion, then the DLL circuit can operate with simpler structure, but half phase locking failures and phase locking misses occur due to power noise and jitter components
Solution Approach 1:
The locking detection function is segmented into multiple parallel phase detection units, each comparing the reference clock with the feedback clock at different phase points. This segmentation allows the system to detect locking status more accurately by examining multiple phase relationships simultaneously, thereby preventing half-phase locking failures while maintaining modular complexity
Solution Approach 2:
The invention transitions from single-point phase comparison to multi-dimensional phase space analysis by introducing multiple phase detection units that operate at different phase offsets. This dimensional expansion enables the system to distinguish between true locking conditions and noise-induced false positives, improving reliability without proportionally increasing complexity
2Reliability
If multiple phase detection units are introduced to improve locking detection accuracy, then half phase locking failures and phase locking misses are prevented, but the device complexity increases
Solution Approach 1:
Multiple phase detection units are merged into a unified locking detection structure where their outputs are logically combined through OR gates. This merging approach allows the system to benefit from multiple phase comparisons while consolidating the detection logic into a compact configuration, thereby improving reliability without linearly increasing overall device complexity
Solution Approach 2:
The phase detection units are designed with universal functionality to handle multiple detection scenarios simultaneously. Each unit can operate independently to detect different locking conditions, and their combined output provides comprehensive locking status information, maximizing the utility of each added component and reducing the effective complexity increase
Data Source
AI summary
The DLL comprises a coarse delay line configured to have a plurality of unit delays and delay an reference dock to output a delayed clock, a fine delay line configured to delay the delayed clock to output a delayed output clock, a replica delay unit configured to delay the delayed output clock by an expected modeling value to output a feedback clock, a phase detection unit configured to compare a phase of the feedback clock with a phase of the reference clock to generate first to third phase detection signals based on a result of the comparison, a locking detection unit configured to output a locking signal by selecting a first locking detection signal or a second locking detection signal, and a control unit configured to control the coarse and fine delay lines in response to the locking signal and the first phase detection signal.