DLL Update Deactivation During Refresh for Stable Phase Lock
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Solution Overview
Problem
In semiconductor memory devices, such as DRAM, the phase lock level in the delay locked loop (DLL) update circuit varies due to changes in temperature, voltage, and load conditions during memory operations like refresh, affecting the DLL's performance and requiring adjustments that can take time, impacting data alignment with external clock signals.
Innovation Solution
The DLL update is deactivated during memory cell array activation, such as during refresh operations, and reactivated when the arrays are deactivated, ensuring that the DLL update circuit only performs adjustments during specific trigger signals, minimizing disruptions and maintaining phase lock stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the DLL update circuit continuously adjusts the phase lock level, then the phase alignment accuracy is improved, but the stability during memory operations deteriorates due to power supply variations
Solution Approach 1:
The system performs DLL updates at predetermined intervals when memory cell arrays are not actively operating. By scheduling updates in advance during idle periods and preventing them during active operations, the system ensures accurate phase alignment without the instability caused by concurrent memory operations and power supply variations.
2Measurement precision
If the DLL update is performed during memory refresh operations, then the phase lock accuracy is maintained, but the performance deteriorates due to power supply voltage changes
Solution Approach 1:
The system dynamically adjusts the timing of DLL updates based on the operational state of memory cell arrays. The update timing is flexibly scheduled to occur during idle periods when power supply conditions are stable, rather than at fixed intervals or during active operations, thereby maintaining both phase lock accuracy and memory operation performance.
Solution Approach 2:
The system proactively schedules DLL updates during predicted idle periods between memory operations. By anticipating when memory arrays will be inactive and scheduling updates in advance, the system ensures phase lock accuracy is maintained without interfering with ongoing memory refresh operations or performance-critical tasks.
3Reliability
If the DLL update circuit operates continuously, then the phase alignment is maintained, but the power consumption increases during high-load operations
Solution Approach 1:
The system performs DLL updates periodically at predetermined intervals rather than continuously. This periodic operation maintains phase alignment reliability by regularly correcting phase drift while significantly reducing average power consumption compared to continuous operation, especially during extended idle periods between memory operations.
Data Source
AI summary
A semiconductor device may include a delay locked loop (DLL) control circuit coupled to an update trigger generator and a DLL update circuit. The DLL control circuit may receive an update trigger signal and an internal refresh signal and configured to activate the DLL update circuit responsive to an update trigger in the update trigger signal and deactivate the DLL update circuit responsive to an active internal refresh signal. The DLL update circuit may perform DLL update to one or more memory cell arrays when activated and not perform DLL update to the memory cell arrays when deactivated. The DLL control circuit may reactivate the DLL update circuit once the internal refresh signal becomes inactive. In other scenarios, once the DLL update circuit is deactivated, the DLL update circuit stays deactivated until the next update trigger in the update trigger signal.