Delay-Locked Loop Circuit Phase Locking Stability
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Solution Overview
Problem
Delay-locked loop circuits often lock into abnormal phase states during start-up or due to external noise, leading to unstable operation and increased power consumption.
Innovation Solution
A delay-locked loop circuit design that includes a phase-detection controller which excludes at least one cycle of clock pulses from the phase detection during mode transition, allowing the phase difference to be set within a prescribed range, and a phase-judgment circuit to assess the phase state and transition-judgment circuit to correct abnormal transitions, ensuring stable locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase detection is continuously performed during mode transition, then the phase detector can detect all phase differences, but the DLL circuit may lock into abnormal phase states
Solution Approach 1:
The patent extracts and excludes clock pulses during mode transition from the phase detection process. The phase-detection controller selectively disables phase detection for specific clock cycles when transitioning between stop and DLL modes, removing the harmful effect of abnormal phase locking during critical transition periods while maintaining normal phase detection during stable operation.
2Measurement precision
If the phase detector detects all clock pulses, then comprehensive phase information is obtained, but power consumption increases during mode transition
Solution Approach 1:
The patent implements periodic phase detection by controlling the phase-detection controller to enable phase detection only during specific operational modes (normal operation) and disable it during mode transitions. This periodic activation reduces power consumption while maintaining necessary phase detection accuracy when actually needed.
3Speed
If mode transition is performed without excluding clock pulses, then the DLL circuit responds quickly to mode changes, but phase locking stability deteriorates
Solution Approach 1:
The patent applies preliminary action by excluding clock pulses from phase detection before the mode transition is complete. The phase-detection controller anticipates the mode transition and disables phase detection for clock pulses occurring during the transition period, preventing abnormal phase locking before it can occur, thus maintaining stability without significantly delaying the mode transition.
Data Source
AI summary
The delay of delay circuit 10 is set within a predetermined range, and, in a stop mode, the clock pulses of 1 cycle of clock signal φin when transition is made from the stop mode to the DLL mode are excluded from the object detected by phase detector 20 such that phase difference Δφ′ detected by phase detector 20 is within a prescribed range when said transition is performed. As a result, it is possible to lock the delay of clock signal φdin with respect to clock signal φin at a desired value (e.g., “2π”), and it is possible to prevent locking to an undesired abnormal state.