DLL Delay Structure With Phase Mixer for Jitter-Free Clock Shifting
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing delay-locked loop (DLL) architectures face challenges in maintaining seamless phase change and controlling coarse shifting at high frequencies, leading to output clock jitter and discontinuity at the boundary of coarse and fine delays.
Innovation Solution
A clock synchronization circuit utilizing a single coarse delay line to generate two intermediate clocks with a fixed phase difference, which are then processed by a phase mixer to produce an output clock that maintains phase integrity, allowing for seamless phase transition and coarse shifting without jitter or noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dual delay line (coarse and fine) architecture is used, then wide lock range and tight lock are achieved, but output clock jitter and phase discontinuity occur at high frequencies
Solution Approach 1:
The patent merges the coarse and fine delay lines into a unified structure where the fine delay line is overlaid on the coarse delay line. This integration allows seamless transition between coarse and fine adjustments, eliminating phase discontinuity and jitter at high frequencies while maintaining wide lock range and tight lock capabilities.
Solution Approach 2:
The patent implements dynamic switching between coarse and fine delay modes based on operating conditions. At high frequencies, the system dynamically transitions to fine-only mode to avoid jitter, while at lower frequencies it utilizes both coarse and fine delays for optimal performance. This dynamic adaptation resolves the contradiction between phase continuity and high-frequency operation.
2Adaptability or versatility
If coarse shifting is performed in traditional DLL architectures, then phase adjustment range is increased, but output clock jitter and noise are introduced
Solution Approach 1:
The patent segments the delay adjustment into distinct coarse and fine components that operate independently but are integrated in their output. The coarse delay line provides large phase steps for wide adjustment range, while the fine delay line provides small continuous steps. By segmenting the adjustment mechanism and integrating the outputs, the system achieves wide phase adjustment range without introducing jitter from coarse shifting.
3Device complexity
If a single delay line is used instead of dual delay lines, then device complexity is reduced, but lock range and locking precision are compromised
Solution Approach 1:
The patent implements a nested structure where the fine delay line is embedded within the coarse delay line framework. The fine delay units are positioned at specific stages of the coarse delay line, allowing both functions to share the same physical structure. This nesting reduces overall device complexity compared to completely separate delay lines while maintaining the precision benefits of fine adjustment.
Data Source
AI summary
A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs.