DLL Phase Mixer with Coarse-Fine Delay for Fast Clock Sync
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Solution Overview
Problem
Conventional delay locked loops (DLLs) in semiconductor memory devices face challenges in achieving fine resolution delay adjustments quickly enough to synchronize internal and external clock phases at high operating speeds, leading to potential distortions in clock signal duty cycles that affect memory access speed and reliability.
Innovation Solution
The implementation of a DLL circuit with a combination of coarse and fine delay lines, along with a phase mixer that uses sets of fine control signals to weight and interpolate the phases of input clock signals, allowing for precise adjustment of the internal clock signal to match the external clock signal, thereby ensuring synchronization and reducing phase shift.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional phase mixer is used to compare external and internal clock phases, then the delay adjustment resolution can be made fine, but the tracking speed becomes slow
Solution Approach 1:
The delay adjustment is segmented into two independent parts: a coarse delay line for fast tracking with large step size, and a fine delay line for precise adjustment with small step size. The coarse delay line quickly reduces the phase difference between external and internal clocks, while the fine delay line provides precise final adjustment. This segmentation allows the system to achieve both fast tracking speed and fine resolution without the trade-off present in conventional single-stage phase mixers.
2Device complexity
If the clock phase is adjusted using a single delay circuit, then the circuit structure remains simple, but the ability to achieve both fast tracking and fine resolution is compromised
Solution Approach 1:
The delay circuit is divided into two separate delay lines: a coarse delay line with larger delay steps for fast initial synchronization, and a fine delay line with smaller delay steps for precise phase matching. This segmentation enables the system to achieve fine resolution phase comparison while maintaining a relatively simple overall structure, as each delay line can be optimized independently for its specific function.
3Measurement precision
If fine resolution delay adjustment is implemented, then the clock phase synchronization accuracy improves, but the time required for phase comparison and adjustment increases
Solution Approach 1:
The phase comparison and adjustment process is divided into two stages: a fast coarse adjustment stage using the coarse delay line that quickly reduces large phase differences, and a slow fine adjustment stage using the fine delay line that precisely matches the remaining small phase difference. This two-stage segmented approach minimizes the total time required for synchronization by handling the time-consuming fine adjustment only after the quick coarse adjustment has brought the phases close together.
Solution Approach 2:
The coarse delay line performs a preliminary action by quickly reducing the large phase difference between external and internal clocks before the fine delay line performs the precise final adjustment. This preliminary coarse adjustment reduces the workload and time required for the subsequent fine adjustment, enabling the system to achieve fine resolution synchronization faster than would be possible with fine adjustment alone.
Data Source
AI summary
Apparatuses and methods for adjusting a phase mixer circuit are disclosed. An example method includes providing data values stored by a plurality of first registers and a plurality of second registers. The method includes: during a first mode of operation, receiving the data values by groups of first registers of the plurality of the first registers and holding the data values by the plurality of second registers; during a second mode of operation, inverting a data value by one first register of the plurality of first registers at a time and holding the data values by the plurality of second registers; and during a third mode of operation, either inverting the data value by one first register of the plurality of first registers while holding the data values by the plurality of second registers or inverting a data value by one second register of the plurality of second registers while holding the data values by the plurality of first registers.