DLL Phase Mixer Delay Control for Fast Fine Clock Alignment
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Solution Overview
Problem
Conventional delay locked loops (DLLs) in semiconductor memory devices face challenges in achieving fine resolution delay adjustments quickly, leading to potential distortions in clock signal duty cycles at high operating speeds, which can affect memory access speed and reliability.
Innovation Solution
The implementation of a DLL circuit with a combination of coarse and fine delay lines, along with a phase mixer that uses sets of fine control signals to weight and interpolate the phases of input clock signals, allowing for precise adjustment of the internal clock signal to synchronize with external clock signals, thereby enhancing tracking speed and resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional phase mixer is used to compare external and internal clock phases, then the delay adjustment resolution is improved, but the tracking speed deteriorates
Solution Approach 1:
The delay line is segmented into multiple taps, each providing a specific delay value. The phase mixer selectively combines signals from these segmented taps to achieve fine delay adjustment resolution while maintaining fast tracking speed through efficient signal combination.
Solution Approach 2:
The phase mixer dynamically adjusts the weighting of input signals based on real-time phase comparison results. This dynamic adjustment allows the system to achieve both fine resolution and fast tracking by adaptively optimizing the delay adjustment process.
2Measurement precision
If the clock phase is adjusted using a delay circuit, then the phase matching accuracy is improved, but the chip size increases
Solution Approach 1:
The delay locked loop circuit performs multiple functions including phase comparison, delay adjustment, and duty cycle correction within a single integrated structure. This multi-functionality achieves high phase matching accuracy without proportionally increasing chip size.
Solution Approach 2:
The delay adjustment mechanism is nested within the existing DLL architecture, with fine delay taps integrated into the delay line structure. This nested design achieves precise phase matching while minimizing additional chip area.
3Reliability
If the duty cycle distortion is accommodated, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The duty cycle correction function is merged with the phase adjustment mechanism in the phase mixer. By combining these functions, the circuit achieves improved reliability through duty cycle distortion accommodation without significantly increasing overall device complexity.
Data Source
AI summary
Apparatuses and methods for adjusting a phase mixer circuit are disclosed. An example method includes providing data values stored by a plurality of first registers and a plurality of second registers. The method includes: during a first mode of operation, receiving the data values by groups of first registers of the plurality of the first registers and holding the data values by the plurality of second registers; during a second mode of operation, inverting a data value by one first register of the plurality of first registers at a time and holding the data values by the plurality of second registers; and during a third mode of operation, either inverting the data value by one first register of the plurality of first registers while holding the data values by the plurality of second registers or inverting a data value by one second register of the plurality of second registers while holding the data values by the plurality of first registers.