Delay-Locked Loop Phase Multiplexing for Faster Low-Power Locking
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Solution Overview
Problem
Existing delay-locked loop devices face inefficiencies due to unnecessary current consumption and area occupation by inactive circuit components, and they require additional locking time due to jitter issues, especially when using dual coarse delay lines.
Innovation Solution
A delay-locked loop device with a rising clock and falling clock delay-locked circuit configuration, utilizing a dual coarse delay line and complementary phase multiplexing to reduce current consumption and area, while maintaining efficient locking operations by selectively activating and deactivating delay lines based on phase differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual delay model portions are used to align clock phases and correct duty cycles, then clock skew compensation and duty cycle correction are improved, but current consumption and circuit area increase
Solution Approach 1:
The patent extracts and removes the second delay model portion from the circuit after the rising edge alignment is achieved. Only the first delay model portion is retained for duty cycle correction operations, eliminating unnecessary current consumption while maintaining clock skew compensation functionality
Solution Approach 2:
The second delay model portion is discarded after completing its function of aligning rising edges. The circuit transitions to using only the first delay model portion for subsequent duty cycle corrections, effectively discarding the redundant component to reduce power consumption
2Loss of time
If dual coarse delay lines are used to reduce locking time, then phase alignment speed is improved, but circuit area and current consumption increase
Solution Approach 1:
The patent implements dynamic switching between single and dual coarse delay line configurations. During initial locking, both coarse delay lines are activated to reduce locking time. After locking is achieved, the circuit dynamically switches to using only one coarse delay line, reducing circuit area and current consumption while maintaining performance
3Measurement precision
If dual delay model portions operate simultaneously for rising and falling edge alignment, then phase detection accuracy is improved, but jitter increases due to switching operations
Solution Approach 1:
The patent employs periodic action by sequentially activating the second delay model portion only during rising edge alignment phases, then deactivating it for falling edge operations. This periodic activation pattern reduces switching frequency and minimizes jitter while maintaining phase detection accuracy when needed
Data Source
AI summary
A delay-locked loop device compensates a skew between an external clock and data or between an external clock and an internal clock particularly by applying a single delay model portion, a complementary phase multiplexing, and a cascade delay line. This device performs an operation by selecting any one of an external clock signal (CLK) and an inverted external clock signal (CLKB) using a multiplexing portion 200, aligning the selected clock signal at a rising edge of the external clock signal (CLK) through a first single coarse delay line 212, a first dual coarse delay line 222, and a first fine delay unit 223 according to the phase comparison with a feedback clock signal (FBCLK) through a delay model portion 250, then receiving a clock signal through the first single coarse delay line 212 to the second single coarse delay line 214 to align the rising edges of the rising clock signal (RCLK) and the falling clock signal (FCLK).