DLL Phase Adjustment Using Pulse-Width-Based Delay Step Selection
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Solution Overview
Problem
Traditional phase locking methods in semiconductor devices are inefficient due to the lack of precise measurement of the external clock period, leading to inefficient selection of delay step size, resulting in a large number of clock cycles required to achieve synchronization, which is time-consuming and may risk over-adjusting the internal clock phase.
Innovation Solution
A semiconductor memory device with a pulse width detection circuit and a delay-locked loop (DLL) that selects a step size for the DLL by comparing the high and low pulse widths of the internal clock signal to determine the largest acceptable step size, ensuring efficient synchronization without over-adjusting the internal clock phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single step size is used for DLL delay adjustment, then the device complexity is reduced, but the synchronization time increases and may cause over-adjustment
Solution Approach 1:
The delay adjustment process is segmented into two distinct phases: coarse adjustment using a first step size to quickly reduce the phase difference, and fine adjustment using a second step size to precisely achieve synchronization. This segmentation allows the system to balance speed and precision without requiring complex real-time step size selection logic.
Solution Approach 2:
The step size is made dynamic by transitioning from a fixed single step size to a two-stage variable step size approach. The system automatically adjusts the step size based on the synchronization stage, using larger steps initially and smaller steps near the target, thereby optimizing both convergence speed and precision without increasing overall system complexity.
2Reliability
If a small step size is used for DLL delay adjustment, then over-adjustment is avoided, but the number of clock cycles required to achieve synchronization increases
Solution Approach 1:
The adjustment process is divided into coarse and fine stages, allowing the system to use larger step sizes during coarse adjustment when over-adjustment risk is lower, and switch to smaller step sizes during fine adjustment when precision is critical. This segmentation enables the system to achieve both fast convergence and high accuracy.
Solution Approach 2:
During coarse adjustment, the system intentionally applies partial excessive action by using larger step sizes that may temporarily overshoot the target phase, but then corrects this in the fine adjustment stage. This approach allows rapid initial convergence followed by precise correction, achieving both speed and accuracy.
3Device complexity
If sequential stepping with single step size is used, then the control logic is simplified, but the synchronization efficiency decreases
Solution Approach 1:
The control logic is segmented into two simple sequential stages rather than requiring complex dynamic step size selection. The first stage uses a fixed first step size for coarse adjustment, and the second stage uses a fixed second step size for fine adjustment. This segmentation maintains logical simplicity while dramatically improving synchronization efficiency.
Solution Approach 2:
The synchronization process uses periodic action by alternating between two distinct adjustment phases with different step sizes. This periodic switching between coarse and fine adjustment modes creates an efficient rhythm that balances speed and precision without requiring complex real-time decision-making logic.
Data Source
AI summary
According to one embodiment, a synchronous semiconductor device is disclosed According to this embodiment, the synchronous semiconductor device includes a pulse width detection circuit to provide detection information responsive to a plurality of delay amounts being different from one another and at least one of a high pulse width and a low pulse width of a first clock signal. The detection information representing relationships in size between each of the plurality of delay amounts and the at least one of the high pulse width and the low pulse width of the first clock signal. A delay line control circuit coupled to the pulse width detection circuit and the delay line. The delay line control circuit configured to change a delay amount of the delay line by a step size determined responsive, at least in part, to the detection information.