Delay-Locked Loop Phase Control Under Supply Voltage Changes
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Solution Overview
Problem
Conventional DLL circuits experience performance reduction and phase misalignment of clock signals due to changes in power supply voltage after locking, leading to increased current consumption when trying to maintain synchronization.
Innovation Solution
Incorporating a phase comparator and signal selector to independently control the second delay line after DLL locking, allowing for phase alignment without activating the second signal processor, thus preventing phase misalignment and reducing current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the second signal processor is activated to maintain phase alignment after DLL locking, then phase synchronization is improved, but current consumption increases
Solution Approach 1:
The patent segments the control function by separating the second signal processor (full functionality) from the phase comparator (simplified function). After DLL locking, only the simplified phase comparator remains active for phase alignment, while the power-intensive second signal processor is deactivated. This segmentation allows phase synchronization to be maintained with minimal current consumption.
Solution Approach 2:
The patent changes the operational parameters of the phase detection mechanism. Before DLL locking, the second signal processor operates with full functionality. After locking, the system transitions to using a simplified phase comparator with reduced functionality, changing the operational state from high-power to low-power mode while maintaining essential phase alignment capability.
2Use of energy by moving object
If the second signal processor is turned off to reduce current consumption, then energy efficiency is improved, but phase misalignment occurs due to power supply voltage changes
Solution Approach 1:
The patent introduces a phase comparator as an intermediary element that bridges the gap between turning off the second signal processor and maintaining phase synchronization. This intermediary component specifically monitors and corrects phase alignment caused by power supply voltage changes, enabling the second signal processor to remain off while phase synchronization is preserved.
Solution Approach 2:
The phase comparator provides continuous feedback regarding phase alignment status between the first and second clock signals. This feedback mechanism detects phase misalignment caused by power supply voltage changes and enables corrective action, allowing the system to maintain synchronization without continuously activating the power-intensive second signal processor.
3Device complexity
If a simplified phase comparator is used instead of the second signal processor after locking, then device complexity is reduced, but adaptability to handle various signal conditions deteriorates
Solution Approach 1:
The patent implements a dynamic configuration where the system uses the full-featured second signal processor before DLL locking to handle various signal conditions, then transitions to the simplified phase comparator after locking when signal conditions are more stable. This dynamic adaptation allows the system to have high adaptability when needed and low complexity when sufficient, optimizing both parameters across different operational phases.
Data Source
AI summary
A Delay Locked Loop (DLL) circuit prevents a malfunction caused by a change of a power supply voltage, and includes a first and a second delay lines and a first and a second signal processors for controlling the first and the second delay lines, and turns off the second signal processor after DLL locking. The DLL circuit further includes a phase comparator for generating a comparison signal notifying which of phases of a first clock signal of the first delay line and a second clock signal of the second delay line precedes the other, and a signal selector for inputting an output of the second signal processor to the second delay line before the DLL locking, and inputting the comparison signal of the phase comparator to the second delay line after the DLL locking.