DRAM Delay Locked Loop Power Control
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Solution Overview
Problem
Memory devices, such as DRAM, face increased power consumption due to the delay locked loop circuit even when operating in standby conditions, as it continues to generate unnecessary system clock signals during precharge or powerdown modes.
Innovation Solution
A memory device with a control module that enables the delay locked loop module only during read or write operations and disables it when transitioning to precharge or powerdown modes, reducing power consumption by controlling the system clock signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the delay locked loop circuit continuously generates system clock signals to ensure high-speed operation capability, then the memory device can perform read/write operations at high speed, but the power consumption increases during standby conditions
Solution Approach 1:
The delay locked loop circuit is designed to dynamically change its operating state based on control signals. During active operations, the circuit operates normally to generate system clock signals for high-speed read/write operations. During standby conditions (precharge or powerdown modes), the circuit transitions to a low-power state by stopping clock signal generation, thus reducing power consumption while maintaining the capability to quickly resume high-speed operation when needed.
2Reliability
If the delay locked loop circuit operates continuously to maintain system clock signal availability, then the memory device can respond quickly to operation commands, but unnecessary power is consumed during precharge and powerdown modes
Solution Approach 1:
The delay locked loop circuit operates in periodic cycles, alternating between active clock generation during operations and inactive low-power state during standby modes. The control module monitors the operational state and periodically activates or deactivates the delay locked loop circuit accordingly, ensuring system reliability when needed while minimizing energy loss during precharge and powerdown modes.
3Measurement precision
If the system clock signal is always generated to ensure accurate signal timings, then high-speed operations can be performed accurately, but power consumption increases during standby conditions
Solution Approach 1:
The system dynamically adjusts clock signal generation based on operational requirements. During active read/write operations, the delay locked loop circuit generates precise system clock signals to ensure accurate signal timing for high-speed operations. During standby conditions, the circuit is deactivated to stop unnecessary power consumption, while the control module ensures smooth transitions to maintain timing accuracy when operations resume.
Data Source
AI summary
A memory device and a control method are disclosed herein. The memory device includes a delay locked loop module, a memory bank module and a control module. The delay locked loop module is configured to generate a system clock signal when enabled by a control signal. The memory bank module is configured to read or write data signals in accordance with the system clock signal and a read command or a write command. The control module configured to receive at least one control command to generate the control signal, wherein the control module disables the delay locked loop module, when the memory bank module goes to a precharge mode or a powerdown mode.