DLL Power-Down Control Using Staged Noise-Suppressed Entry
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Solution Overview
Problem
Conventional DLL circuits in semiconductor integrated circuits face noise issues and instability during power-down mode, leading to erroneous operations and inadequate low power consumption support.
Innovation Solution
A power-down mode control apparatus that includes an internal power-down control block, noise check block, and power-down enter control block, which generate signals to manage the entrance of constituent elements into power-down mode based on noise detection and locking completion signals, thereby minimizing noise occurrence and ensuring stable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If multiple constituent elements stop operations simultaneously in response to power-down mode signal, then power consumption is reduced, but noise occurs due to rapid state change causing unstable clock signal
Solution Approach 1:
The power-down mode operation is segmented into multiple stages: a first group of constituent elements (phase detection apparatus, delay control apparatus) stops first, followed by a second group (DLL circuit, clock signal generator) stopping afterward. This staged segmentation prevents simultaneous state changes that cause noise, while still achieving comprehensive power savings when power-down mode is activated.
2Loss of energy
If DLL circuit activates power-down mode to reduce power consumption, then energy loss is reduced, but erroneous operation occurs due to noise and phase distortion
Solution Approach 1:
Before the DLL circuit and clock signal generator stop operations, the phase detection apparatus and delay control apparatus are made to stop first in advance. This preliminary action prepares the system in a controlled state, preventing noise and phase distortion that would otherwise occur during power-down mode activation, thereby ensuring stable operation while maintaining low power consumption.
3Loss of energy
If conventional DLL circuit simultaneously stops constituent elements during power-down mode, then power consumption is reduced, but noise check is insufficient leading to erroneous operation
Solution Approach 1:
A noise check block continuously monitors the clock signal for noise during power-down mode operation. When noise is detected, the system provides feedback to adjust the power-down mode control, preventing erroneous operations. This feedback mechanism enables the system to maintain low power consumption while actively detecting and responding to noise conditions that would otherwise cause instability.
Data Source
AI summary
A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.