DLL Power-Down Sequencing for Stable Clock Signals
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Solution Overview
Problem
Conventional DLL circuits in semiconductor integrated circuits experience noise and unstable clock signals during power-down mode due to rapid state changes, leading to erroneous operations and insufficient low power consumption support.
Innovation Solution
A power-down mode control apparatus and DLL circuit that include an internal power-down control block, noise check block, and power-down enter control block to manage power-down signals and phase detection, minimizing noise occurrence by selectively disabling circuit elements based on noise detection and phase differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If multiple constituent elements are stopped simultaneously in response to the power-down mode signal, then power consumption is reduced, but noise occurs due to rapid state changes causing unstable clock signals
Solution Approach 1:
The power-down mode operation is divided into multiple sequential stages: a first power-down mode where only the delay locked loop circuit stops, and a second power-down mode where additional circuits stop. This segmentation prevents simultaneous state changes of all circuits, reducing noise while achieving power savings.
Solution Approach 2:
The delay locked loop circuit is stopped first as a preliminary action before stopping other circuits. This preliminary power-down sequence allows the system to enter a stable state gradually, preventing noise generation from simultaneous switching while still achieving significant power reduction.
2Ease of operation
If the power-down mode is terminated, then normal operation is restored, but the delay value changes causing phase distortion in the clock signal
Solution Approach 1:
Before terminating the power-down mode, the delay locked loop circuit is activated again as a preliminary action to restore the correct delay value. This ensures that when normal operation resumes, the clock signal phase is accurate and undistorted.
Solution Approach 2:
The system uses phase detection feedback to monitor the clock signal phase and automatically adjust the delay value when exiting power-down mode. This feedback mechanism ensures phase accuracy is maintained during mode transitions.
3Loss of energy
If the DLL circuit stops all constituent elements simultaneously, then power consumption is minimized, but erroneous operation occurs in downstream circuits
Solution Approach 1:
The power-down operation is segmented into selective stopping of circuits: the delay locked loop circuit stops first, while downstream circuits remain operational. This selective segmentation ensures downstream circuits continue to function correctly while still achieving power reduction.
Solution Approach 2:
Different circuits are assigned different power-down behaviors: the delay locked loop circuit enters power-down mode while downstream circuits maintain normal operation. This local differentiation ensures that circuits requiring clock signals continue to operate correctly while the DLL circuit consumes minimal power.
Data Source
AI summary
A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.