DLL Power Control Circuit for Periodic Feedback Loop Gating
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Solution Overview
Problem
Semiconductor integrated circuits face inefficiencies in power consumption due to continuous activation of the feedback loop in DLL circuits after locking is completed, which is undesirable for low-power applications.
Innovation Solution
A power control circuit that includes a check unit, phase detecting unit, and signal combining unit to generate a power cutoff signal upon locking completion, allowing cyclic activation of the feedback loop and re-evaluation of phase differences to determine continued power supply to the delay compensating and clock generating blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the feedback loop is continuously activated after locking is completed, then the DLL circuit maintains clock synchronization, but power consumption increases
Solution Approach 1:
The feedback loop is activated periodically rather than continuously. A power control circuit generates a power cutoff signal that periodically enables the feedback loop to perform phase comparison and delay adjustment, while disabling it during intervals when locking is completed. This periodic activation maintains clock synchronization reliability while significantly reducing power consumption during stable operation.
Solution Approach 2:
The patent changes the operational state parameter of the feedback loop from continuous activation to periodic activation. By controlling the power supply state of the feedback loop through a power cutoff signal, the system transitions between active (during locking) and inactive (after locking) states, optimizing the balance between synchronization reliability and power consumption.
2Use of energy by moving object
If power is cut off to the delay compensating block and clock generating block after locking, then power consumption is reduced, but the ability to respond to phase drift is lost
Solution Approach 1:
The power cutoff signal periodically enables the feedback loop to perform phase comparison and delay adjustment, while disabling it during intervals when locking is completed. This periodic activation maintains clock synchronization reliability while significantly reducing power consumption during stable operation.
Solution Approach 2:
The patent implements a feedback mechanism where the phase comparing block continuously monitors the phase difference between reference clock and feedback clock, and the power control circuit uses this information to control power supply. When phase drift is detected, the feedback loop is reactivated to restore synchronization, ensuring reliability while minimizing power consumption during stable states.
Data Source
AI summary
A method of controlling a power control circuit includes enabling a power cutoff signal when a delay locking operation of a Delay Locked Loop (DLL) circuit is completed, disabling the power cutoff signal for a predetermined time, and detecting a phase difference between a reference clock and a feedback clock to re-determine, on the basis of the detection result, whether or not to enable the power cutoff signal.