DLL Clock Update Control During Power-Down Phase Drift
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Solution Overview
Problem
Conventional semiconductor integrated circuits experience instability and errors during power down mode due to changes in voltage and temperature, leading to incorrect updates of the DLL circuit when the external clock signal frequency changes or is not properly transmitted.
Innovation Solution
A semiconductor integrated circuit with a DLL controller that detects phase changes in the external clock signal and decides whether to activate the DLL, using a phase comparing part to generate a delay locked clock signal only when the phase change is within a predetermined range, thereby preventing errors and maintaining circuit stability during power down mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DLL circuit continuously updates the delay locked clock signal during power down mode, then the clock signal can be periodically updated, but errors occur when the external clock signal frequency changes or is not properly transmitted
Solution Approach 1:
The patent implements a feedback mechanism where the phase comparing part continuously monitors the external clock signal and compares its phase with the internal reference clock signal. When the phase difference exceeds a predetermined threshold, the feedback signal stops the DLL circuit from updating, preventing wrong information from being processed while allowing normal updates when the clock signal is correct.
Solution Approach 2:
The patent performs preliminary verification of the external clock signal's phase before allowing the DLL circuit to update. By checking whether the phase difference is within the acceptable range in advance, the system prevents incorrect updates from occurring, ensuring that only valid clock signal information is processed.
2Use of energy by moving object
If the DLL circuit stops updating during power down mode, then current consumption is reduced, but timing skew cannot be synchronized
Solution Approach 1:
The patent implements periodic updating of the DLL circuit during power down mode, controlled by a power down mode signal. Instead of continuous updating, the system periodically checks and updates the clock signal synchronization only when necessary, reducing current consumption while maintaining timing synchronization capability when needed.
3Reliability
If the DLL circuit updates with every external clock signal, then the clock signal is continuously synchronized, but wrong information is processed when frequency changes occur
Solution Approach 1:
The phase comparing part provides feedback control by monitoring the phase difference between external and internal clock signals. When the phase difference is within the acceptable range, updates are permitted; when it exceeds the threshold, updates are blocked, preventing propagation of incorrect phase information while maintaining synchronization.
Solution Approach 2:
The patent changes the operational parameters of the DLL circuit based on the phase difference condition. By dynamically adjusting whether updates occur based on the predetermined phase threshold, the system ensures reliable synchronization only when the clock signal parameters are within acceptable ranges.
Data Source
AI summary
A semiconductor integrated circuit is disclosed. The disclosed semiconductor integrated circuit of the present invention includes a DLL (Delay Locked Loop) controller that controls whether to activate a DLL at the entry of a power down mode, in response to a result of detecting whether a range of phase change of an external clock signal is within a predetermined range, and a DLL block that provides a result of comparing a reference clock signal with a feedback clock signal to the DLL controller and also provides a delay locked clock signal that is periodically updated, in response to the reference clock signal, under the control of an activated output signal from the DLL controller.