Delay-Locked Loop Clock Update During Power-Down Mode
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Solution Overview
Problem
The DLL circuit in semiconductor memory devices experiences locking failures due to changes in external circumstances, such as temperature, when in a power down mode for an extended period, leading to phase mismatch between the external and internal clock signals, which affects data transmission reliability.
Innovation Solution
A DLL circuit with a source clock generation unit that generates a DLL source clock signal based on a power down mode control signal, allowing for phase update operations in both normal and power down modes, using a clock buffer, power down mode controller, and phase update unit to maintain synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the DLL circuit enters power down mode to reduce power consumption, then power consumption is reduced, but locking failures occur due to phase mismatch between external and internal clock signals
Solution Approach 1:
The patent applies preliminary action by performing a phase update operation before exiting power down mode. Specifically, the phase comparator compares the external clock signal with the internal clock signal to detect phase difference, and the delay controller adjusts the delay amount in advance before normal operation resumes. This ensures that the DLL circuit achieves proper phase synchronization before full operation begins, preventing locking failures while maintaining power savings during idle periods.
2Reliability
If the DLL circuit maintains continuous clock operation to prevent phase mismatch, then locking reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by alternating between power down mode and active mode based on operational needs. The DLL circuit enters power down mode during idle periods to conserve power, and exits to active mode when data transmission is required. The phase update operation is performed periodically at the transition point, ensuring synchronization is maintained only when necessary, thus achieving a balance between power consumption and phase synchronization reliability.
3Measurement precision
If the delay amount is adjusted frequently to maintain phase synchronization, then phase accuracy is improved, but circuit complexity increases
Solution Approach 1:
The patent applies feedback by using the phase comparator to continuously monitor the phase difference between external and internal clock signals. The delay controller receives feedback information about the phase difference and automatically adjusts the delay amount in the delay line accordingly. This closed-loop feedback mechanism maintains high phase accuracy without requiring complex external control circuits, as the system self-regulates based on real-time phase error detection.
Data Source
AI summary
A DLL of a memory device having a normal mode and a power down mode includes a clock buffer for buffering an external clock signal to output an internal clock signal. A power down mode controller generates a power down mode control signal to define the normal mode or the power down mode in response to a clock enable signal. A source clock generation unit receives the internal clock signal to generate a DLL source clock signal under the control of the power down mode control signal. A phase update unit performs a phase update operation based on the DLL source clock signal to output a DLL clock signal.