DLL Clock Initialization Using Precharge for Stable Phase Lock
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Solution Overview
Problem
During the initial operation of DLL circuits, the control voltage level is at ground potential, leading to erroneous operations due to the inability to advance or delay the phase of the feedback clock correctly, resulting in unstable phase synchronization with the reference clock.
Innovation Solution
A DLL circuit with a clock selection control unit generating a clock selection signal and an initialization signal, and a delay control unit that uses an initial voltage generated from the external power supply to create a control voltage, enabling proper phase adjustment by controlling the delay operation, ensuring the control voltage has a higher level than ground voltage during initialization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the control voltage is at ground potential during initial operation, then the circuit structure is simple, but the phase synchronization becomes erroneous and unstable
Solution Approach 1:
The patent applies preliminary action by generating an initial voltage from the external power supply voltage before the DLL circuit begins normal operation. This initial voltage is stored in a capacitor and then applied to the delay line during the initialization phase, ensuring that the delay line receives a valid voltage level (higher than ground) before phase comparison and synchronization operations commence. This prevents erroneous operation during the critical initial startup phase while maintaining circuit simplicity.
2Use of energy by moving object
If the control voltage level is at ground voltage during initial operation, then the circuit operates with minimal power consumption, but the delay line cannot properly advance or delay the feedback clock phase
Solution Approach 1:
The patent generates an initial voltage from the external power supply voltage and stores it in a capacitor before normal operation. This initial voltage is applied to the delay line during initialization, enabling proper phase adjustment capability from the very first operation. The circuit transitions from this preliminary voltage state to normal ground-referenced operation, ensuring phase adjustment works correctly during the critical startup phase without requiring continuous high power consumption.
3Device complexity
If no initialization voltage is provided, then the circuit design is simpler, but erroneous operation occurs during initial conditions
Solution Approach 1:
The patent implements preliminary action by creating an initialization circuit that generates an initial voltage from the external power supply voltage before the DLL circuit begins operation. This initial voltage is stored in a capacitor and applied to the delay line during startup. The initialization signal controls the switching between the initial voltage and the normal control voltage. This approach ensures reliable initial operation while keeping the initialization circuitry minimal and integrated within the existing DLL structure.
4Measurement precision
If the control voltage remains at ground level, then the phase comparison output is ambiguous, but adding voltage control increases circuit complexity
Solution Approach 1:
The patent applies preliminary action by generating an initial voltage from the external power supply voltage and storing it in a capacitor before phase comparison operations begin. This initial voltage is applied to the delay line during initialization, ensuring that the delay line operates at a valid voltage level that enables accurate phase comparison between the reference clock and feedback clock. The voltage control mechanism is kept simple by using the existing power supply voltage divided by a resistor network, avoiding complex voltage generation circuits while achieving precise phase comparison capability from startup.
Data Source
AI summary
A DLL circuit includes a clock selection control unit configured to generate a clock selection signal on the basis of a phase difference between a reference clock and a feedback clock and, after the clock selection signal is generated, to generate an initialization signal. A delay control unit, when the initialization signal is enabled, transfers an initial voltage to be generated by dividing an external power supply voltage to a delay unit as a control voltage, and controls a delay operation of a delay reference clock to be selected on the basis of the clock selection signal.