DLL Initialization Circuit Using Propagation Control for High Frequency
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Solution Overview
Problem
The initialization of delay lock loop circuits in integrated circuits, such as dynamic random access memory devices, becomes complex and difficult as system clock frequencies increase, particularly due to the dependence on signal pulse width for synchronization.
Innovation Solution
A propagation control circuit is introduced between delay elements to selectively filter signal state transitions and prevent them from propagating into the measured delay elements, allowing for initialization without reliance on pulse width, using a reset signal to manage clock signal edges and load shift registers efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional initialization circuitry is used to pre-load shifting circuitry and establish initial delay amount, then the DLL can be initialized, but the circuit complexity increases and operational difficulties arise as system clock frequencies increase
Solution Approach 1:
The patent extracts the propagation control function from the traditional complex initialization circuitry and implements it through a dedicated propagation control circuit that selectively filters signal state transitions. This separation allows the initialization process to be simpler while maintaining reliability at high clock frequencies, as the propagation control circuit independently manages the filtering of clock signal edges without requiring complex initialization sequences
Solution Approach 2:
The patent changes the approach from relying on pulse width parameters to using edge-based propagation control. By filtering based on clock signal edges rather than pulse width, the circuit maintains robust initialization at high frequencies where pulse width becomes unreliable. The propagation control circuit uses reset signals to manage edge detection and filtering, eliminating the need for complex pulse width timing circuits
2Speed
If traditional propagation control is used that relies on signal pulse width for synchronization, then the DLL can track clock signals, but synchronization errors increase at higher clock speeds
Solution Approach 1:
The patent employs periodic action by using the reset signal to periodically clear the propagation control circuit and enable selective filtering of clock signal edges. This periodic resetting ensures that only valid edges are propagated to the delay elements, maintaining synchronization accuracy even at high clock frequencies where continuous pulse width monitoring would fail
Solution Approach 2:
The propagation control circuit acts as an intermediary between the clock signal source and the delay elements. It mediates the transmission of clock edges by selectively filtering them based on the reset signal state, thereby protecting the delay elements from spurious transitions while allowing valid clock edges to pass through. This intermediary function maintains synchronization precision without requiring direct pulse width measurement
3Device complexity
If the buffer region is not isolated from remaining delay elements, then the circuit structure is simpler, but signal state transitions propagate incorrectly causing initialization errors
Solution Approach 1:
The patent segments the delay element chain into a buffer region and remaining delay elements, with the propagation control circuit positioned between them. This segmentation allows the buffer region to be initialized independently without affecting the remaining delay elements. The simple structural addition of the propagation control circuit enables precise control over signal propagation, ensuring that buffer region transitions do not incorrectly propagate to other delay elements during initialization
Data Source
AI summary
A memory device, delay lock loop circuit (DLL) and DLL reset circuitry are described. The DLL includes a shift register and a measured delay for pre-loading the shift register. The reset circuitry selectively filters a clock signal propagation through the measured delay during a reset operation.