High-Frequency DLL Pulse-Width Conditioning for Stable Clock Output
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Solution Overview
Problem
High-frequency delay-locked loops with small duty cycles face signal loss due to duty cycle distortion in existing DLL/DCC circuit structures, where input clocks with narrow pulse widths disappear after passing through delay chains, leading to errors in output clocks.
Innovation Solution
A high-frequency delay-locked loop with a pulse generating circuit that adjusts the input clock to a fixed pulse width, ensuring the pulse width is not smaller than the minimum required by the DLL circuit, preventing signal loss and distortion by controlling the delay time, and maintaining phase and period integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the input clock has a high frequency and small duty cycle, then the clock processing speed is improved, but the signal is lost after passing through the delay chains due to duty cycle distortion
Solution Approach 1:
The pulse width adjustment circuit performs preliminary action by adjusting the pulse width of the input clock signal before it enters the delay chains. This ensures that the signal has sufficient pulse width to withstand the delay process without being lost, thereby preventing signal loss while maintaining high-frequency operation capability
Solution Approach 2:
The invention changes the parameter of pulse width dynamically. The pulse width adjustment circuit modifies the pulse width parameter of the input clock signal based on the minimum pulse width requirements of the delay chains, allowing the system to handle high-frequency signals with small original duty cycles by expanding their pulse width to acceptable levels
2Adaptability or versatility
If the pulse width of the input clock is reduced to achieve smaller duty cycle, then the clock frequency range is expanded, but the signal disappears after delay chains due to insufficient pulse width
Solution Approach 1:
The pulse width adjustment circuit performs preliminary action by adjusting the pulse width of the input clock signal before it enters the delay chains. This ensures that the signal has sufficient pulse width to withstand the delay process without being lost, thereby preventing signal loss while maintaining high-frequency operation capability
Solution Approach 2:
The invention changes the parameter of pulse width dynamically. The pulse width adjustment circuit modifies the pulse width parameter of the input clock signal based on the minimum pulse width requirements of the delay chains, allowing the system to handle high-frequency signals with small original duty cycles by expanding their pulse width to acceptable levels
Data Source
AI summary
The present invention provides a high-frequency delay-locked loop and a clock processing method for the high-frequency delay-locked loop. The high-frequency delay-locked loop comprises a DLL circuit and a DCC circuit that are sequentially connected in series, and a pulse generating circuit used for generating a clock having a fixed pulse width. The fixed pulse width is a high-level width of the clock having the fixed pulse width and not smaller than a minimum pulse width required by the DLL circuit. The fixed pulse width enables a low-level width of the clock having the fixed pulse width to be not smaller than the minimum pulse width required by the DLL circuit. The clock having the fixed pulse width is input into the DLL circuit.