Delay-Locked Loop Circuit with Pulse-Width Adjustment for Wide Delay Range
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing delay-locked loop (DLL) circuits have a limited delay range and become unstable with variations in power supply voltage, making them unsuitable for wide-band applications.
Innovation Solution
A DLL circuit with a control voltage generator, pulse width adjuster, and delay unit that adjusts the pulse width of the input clock based on delay differences, using a charge pump and current source generator to maintain stability across varying power supply voltages, and includes multiple delay lines activated by a control signal to extend the delay range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the delay range of the DLL circuit is increased to support wide-band applications, then the adaptability is improved, but the device complexity increases due to the need for multiple delay lines and pulse width adjustment mechanisms
Solution Approach 1:
The delay line is divided into multiple segments with different delay characteristics. Each segment can be independently controlled to provide different delay values, enabling the circuit to cover a wide delay range while keeping each individual segment relatively simple.
Solution Approach 2:
The pulse width of the input clock is dynamically adjusted based on the selected delay line segment. This dynamic adjustment allows the circuit to adapt to different delay requirements without requiring a completely different circuit configuration for each case.
2Adaptability or versatility
If the power supply voltage varies, then the ease of operation is improved for different operating conditions, but the stability deteriorates as the phase error varies with voltage changes
Solution Approach 1:
The circuit incorporates feedback mechanisms that monitor the phase error and adjust the delay accordingly. This feedback loop compensates for voltage-induced phase errors, maintaining stable operation across different power supply voltages.
Solution Approach 2:
The circuit changes its operating parameters (such as delay line selection and pulse width adjustment) based on the detected phase error. This adaptive parameter adjustment ensures that the circuit maintains stability even when power supply voltage varies.
Data Source
AI summary
A delay-locked loop (DDL) circuit and a semiconductor device including the same are provided. The DDL circuit includes: a control voltage generator for generating a control voltage corresponding to a delay difference between an input clock and a plurality of comparison clocks by comparing the input clock with the plurality of comparison clocks that are sequentially generated and have different delays; a pulse width adjuster for adjusting a pulse width of the input clock according to a delay difference between the input clock and an arbitrary comparison clock of the comparison clocks and for generating a pulse-width-adjusted input clock as an adjusted input clock; and a delay unit for delaying the adjusted input clock in response to the control voltage and for outputting the delayed adjusted input clock as the comparison clocks and output clocks.