DLL Quiescence Control for Stable Clock Phase and Lower Power
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Solution Overview
Problem
As SDRAM bandwidths increase, differential signal propagation delays can cause a loss of synchronization between data bits and clocks, which existing delay-locked loop (DLL) circuits struggle to mitigate effectively, leading to power consumption issues and timing ambiguities.
Innovation Solution
The implementation of a quiescence mode for DLL or PLL circuits that maintains a steady state by breaking the feedback loop after synchronization is achieved, allowing for reduced power consumption and stable clock phase control, using a variable delay line, delay control module, and phase detector to select and maintain a desired phase relationship, and enabling quiescence operations through a quiescence control module.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DLL circuits continuously adjust delay to maintain synchronization, then synchronization between data and clocks is improved, but power consumption increases
Solution Approach 1:
The DLL is operated in a quiescent mode where the delay element holds a fixed delay value after initial synchronization is achieved. The feedback loop is effectively disabled during normal operation, and only periodic adjustments are made when re-synchronization is needed, rather than continuous adjustment. This reduces power consumption while maintaining synchronization.
Solution Approach 2:
The system performs synchronization adjustments in advance during initialization or when synchronization is lost, then maintains the predetermined delay value without continuous adjustment. The delay element is pre-configured to hold the correct delay value, and the system only intervenes when re-synchronization is required.
2Measurement precision
If DLL circuits operate in closed-loop mode to maintain synchronization, then timing accuracy is improved, but timing variables and testing complexity increase
Solution Approach 1:
The feedback loop is extracted or disabled during normal operation, transitioning the DLL from closed-loop to open-loop quiescent mode. This removes the dynamic feedback mechanism that introduces timing variables, simplifying the system behavior and making testing easier while maintaining the synchronization achieved during the locked state.
Solution Approach 2:
The DLL dynamically switches between two operational states: a locked state with active feedback loop for achieving synchronization, and a quiescent state with disabled feedback loop for stable, low-power operation. This dynamic state transition allows the system to have timing accuracy when needed while avoiding timing variables during normal operation.
Data Source
AI summary
Apparatus, systems, and methods disclosed herein may initialize a delay-locked loop (DLL) or phase-locked loop (PLL) to achieve a locked condition and may then initiate a quiescent mode of operation. Quiescent operation may be achieved by breaking a feedback loop associated with the DLL or PLL to prevent updates to a variable delay line associated with the DLL and/or to a variable frequency oscillator associated with the PLL. An output clock phase associated with the DLL or PLL may thus be held substantially constant following a DLL initialization period. Additional embodiments are disclosed and claimed.