DLL Update Gating During DRAM Refresh for Stable Phase Lock
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Solution Overview
Problem
In semiconductor memory devices, such as DRAM, the phase lock level in the delay locked loop (DLL) update circuit varies due to changes in temperature, voltage, and load conditions during memory operations like refresh, affecting the DLL's performance and requiring adjustments that can take time, impacting data alignment with external clock signals.
Innovation Solution
A DLL control circuit is configured to deactivate the DLL update during memory cell array activation, such as during refresh operations, and reactivate it when the arrays are deactivated, ensuring minimal disruption to phase lock adjustments and maintaining optimal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the DLL update circuit continuously adjusts the phase lock level, then the phase alignment accuracy is improved, but the stability of the DLL is worsened during memory refresh operations due to power supply fluctuations
Solution Approach 1:
The system performs DLL updates at predetermined intervals when memory cell arrays are not activated, preparing the phase lock level in advance before memory operations begin. This preliminary action ensures that the DLL is optimized before potential power supply disturbances occur during refresh operations.
Solution Approach 2:
The patent extracts the DLL update function from continuous operation and separates it into discrete update cycles that occur only when memory arrays are inactive. This extraction prevents the DLL update circuit from being affected by power supply fluctuations during memory refresh operations.
2Speed
If the DLL update circuit operates continuously, then the phase lock adjustment speed is improved, but the reliability of the phase lock level is worsened during memory refresh operations
Solution Approach 1:
The DLL update circuit operates periodically at predetermined intervals rather than continuously, synchronizing its operation with memory operation cycles. This periodic action ensures that updates occur during stable periods when power supply voltage is constant, improving reliability while maintaining adequate adjustment speed.
Solution Approach 2:
The system performs DLL updates in advance before memory refresh operations begin, ensuring that the phase lock level is optimized before potential disturbances occur. This preliminary adjustment maintains reliability by completing updates during stable conditions.
3Productivity
If the DLL update is performed during memory refresh operations, then the overall system responsiveness is improved, but the manufacturing precision of the phase lock level is worsened due to power supply changes
Solution Approach 1:
The patent extracts the DLL update operation from periods when memory refresh is occurring and schedules it for when memory arrays are inactive. This separation ensures that phase lock level adjustments are performed under stable power supply conditions, guaranteeing precision without compromising overall system responsiveness.
Solution Approach 2:
The system implements periodic DLL updates that are synchronized with memory operation cycles, performing updates during stable intervals between refresh operations. This periodic scheduling maintains precision by avoiding power supply fluctuations while preserving system responsiveness through regular updates.
4Stability of the object's composition
If the DLL update circuit is deactivated during memory operations, then the stability of the phase lock level is improved, but the adaptability of the DLL to changing conditions is worsened
Solution Approach 1:
The DLL update circuit is activated periodically at predetermined intervals rather than remaining continuously active or completely deactivated. This periodic activation maintains stability during memory operations while preserving adaptability by allowing the DLL to adjust to changing conditions at regular intervals when power supply is stable.
Solution Approach 2:
The system performs DLL updates in advance before memory operations begin and at predetermined intervals thereafter, ensuring the DLL adapts to changing conditions proactively rather than reactively. This preliminary and periodic action maintains both stability during operations and adaptability to changing conditions.
Data Source
AI summary
A semiconductor device may include a delay locked loop (DLL) control circuit coupled to an update trigger generator and a DLL update circuit. The DLL control circuit may receive an update trigger signal and an internal refresh signal and configured to activate the DLL update circuit responsive to an update trigger in the update trigger signal and deactivate the DLL update circuit responsive to an active internal refresh signal. The DLL update circuit may perform DLL update to one or more memory cell arrays when activated and not perform DLL update to the memory cell arrays when deactivated. The DLL control circuit may reactivate the DLL update circuit once the internal refresh signal becomes inactive. In other scenarios, once the DLL update circuit is deactivated, the DLL update circuit stays deactivated until the next update trigger in the update trigger signal.