DLL Clock Re-Locking with Dynamic Delay Control Under Power Noise
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Solution Overview
Problem
Memory devices face challenges in rapidly locking clocks in power noise situations, leading to increased locking times and reduced data valid windows due to the conventional delay locked loop (DLL) operations, which perform coarse and fine locking operations sequentially and re-lock using fine locking after power drops.
Innovation Solution
A memory device with a DLL that includes a first and second delay line, controllers for generating code values based on phase differences, phase detectors, a de-multiplexer, and a window detection circuit to monitor clock skew and dynamically perform coarse locking operations in response to power noise, allowing for quick synchronization of clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional DLL performs coarse and fine locking operations sequentially, then the delay resolution is improved, but the clock locking time is increased
Solution Approach 1:
The delay line is divided into a coarse delay line and a fine delay line, with separate controllers that can operate independently or together. This segmentation allows the system to perform coarse locking quickly using the coarse delay line, then switch to fine delay line for precision adjustments, reducing total locking time while maintaining high delay resolution
Solution Approach 2:
The DLL system dynamically switches between coarse and fine delay lines based on operational needs. The first delay line controller and second delay line controller can be selectively activated, allowing the system to transition from high-speed coarse locking to high-precision fine locking, optimizing both speed and accuracy at different stages
2Measurement precision
If a conventional DLL performs fine locking operation after power drop, then the clock synchronization accuracy is improved, but the re-locking time is increased
Solution Approach 1:
The coarse delay line is pre-configured with delay elements that can provide initial clock synchronization quickly after power drop or reset. This preliminary coarse locking action establishes a baseline synchronization before fine delay line adjustments are made, significantly reducing the time required to re-establish clock synchronization after power disturbances
Solution Approach 2:
The system changes the operational parameters of the delay lines based on power status. When power is restored after a drop, the system initially uses the coarse delay line with larger delay steps for rapid re-locking, then transitions to the fine delay line with smaller delay steps for precision synchronization, adapting the delay resolution parameter to the operational context
3Measurement precision
If a DLL uses a single delay line with high delay resolution, then the clock synchronization precision is improved, but the locking speed is reduced
Solution Approach 1:
The delay line is segmented into two functional parts: a coarse delay line with lower resolution but faster response, and a fine delay line with higher resolution but slower response. This segmentation allows the system to leverage the speed advantage of the coarse line for initial locking while using the precision advantage of the fine line for final synchronization, achieving both high speed and high precision
4Device complexity
If a DLL does not monitor clock skew dynamically, then the device complexity is reduced, but the data valid window is reduced due to power noise
Solution Approach 1:
A window detection circuit is implemented to continuously monitor clock skew between the reference clock and feedback clock. This feedback mechanism detects when clock skew exceeds acceptable thresholds and triggers appropriate corrective actions, ensuring that data valid windows remain sufficient even in the presence of power noise, while adding only minimal circuit complexity
Data Source
AI summary
A clock locking method of a memory device, may include performing an initial locking operation in a delay locked loop circuit before an internal voltage is stabilized, monitoring clock skew between a reference clock and a feedback clock using a window detection circuit after the internal voltage is stabilized, and performing a re-locking operation in the delay locked loop circuit using a dynamic delay control corresponding to the clock skew.