Delay-Locked Loop Replica Delay for Wide Frequency Synchronization
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Solution Overview
Problem
Conventional delay locked loops (DLLs) face challenges in synchronizing internal clocks with external clocks across varying frequencies, leading to increased area and current consumption, especially during low-frequency operations, which results in jitter issues.
Innovation Solution
The proposed DLL includes a first delay unit, a replica delay unit, and a delay amount control unit that adjust the delay amount by comparing the input clock phase with the feedback clock phase, and an operational frequency detection unit to dynamically adjust the delay by adding an additional delay amount during low-frequency operations, thereby extending the operational frequency range without increasing area or current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the delay amount is increased to extend the operational frequency range during low-frequency operations, then the operational frequency range is extended, but the area and current consumption increase
Solution Approach 1:
The patent applies dynamics by making the delay amount adjustable based on operational frequency. The delay locked loop dynamically changes the delay amount according to the detected frequency range, using a first delay amount for high-frequency operations and a second, larger delay amount for low-frequency operations. This dynamic adjustment extends the operational frequency range without requiring a permanently large delay circuit that would consume area and power at all times.
Solution Approach 2:
The patent changes the delay parameter based on operational conditions. By detecting the operational frequency and switching between different delay amounts (first delay amount for high-frequency, second delay amount for low-frequency), the system adapts to different frequency ranges without permanently increasing circuit area or power consumption. The delay amount is a controllable parameter that varies with operating conditions.
2Adaptability or versatility
If the delay amount is increased to extend the operational frequency range during low-frequency operations, then the operational frequency range is extended, but the current consumption increases
Solution Approach 1:
The system dynamically adjusts the delay amount based on detected frequency, using a larger second delay amount only when low-frequency operation is detected. This prevents continuous high current consumption that would occur if the larger delay circuit were always active, while still enabling extended frequency range when needed.
Solution Approach 2:
The delay amount parameter is changed based on operational frequency detection. The system switches between a first delay amount and a second delay amount depending on whether high-frequency or low-frequency operation is detected, optimizing the balance between frequency range and power consumption.
3Adaptability or versatility
If the delay unit is designed to handle low-frequency operations with extended delay amount, then the operational frequency range is extended, but the jitter increases
Solution Approach 1:
The patent uses dynamic adjustment of delay amount based on frequency detection. By switching to the second delay amount only during low-frequency operations and using the first delay amount during high-frequency operations, the system maintains timing precision and reduces jitter for each operating condition rather than using a fixed large delay that would cause jitter across all frequencies.
Solution Approach 2:
The delay parameter is optimized for different frequency ranges by changing the delay amount based on detected operational frequency. This parameter adaptation reduces jitter by matching the delay characteristics to the specific operating conditions rather than using a suboptimal fixed delay setting.
Data Source
AI summary
A delay locked loop includes a first delay unit configured to output an output clock by delaying an input clock by a delay; a replica delay unit configured to output a feedback clock by delaying the output clock with a delay equal to a sum of a first delay amount for a first operational frequency of the delayed locked loop and an additional delay amount for a second operational frequency of the delayed locked loop, wherein the second operational frequency is lower than the first operational frequency; and a delay amount control unit configured to control the delay of the first delay unit by comparing a phase of the input clock with a phase of the feedback clock.