Delay-Locked Loop Replica Timing for One-Cycle Phase Locking
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Solution Overview
Problem
The delay locked loop circuit in semiconductor devices experiences longer update times and increased jitter when handling high-frequency clock signals, leading to difficulties in completing the delay locking operation within a desired timeframe due to the phase comparator comparing phases that are not completely updated, resulting in synchronization issues between the feedback and source clocks.
Innovation Solution
A delay locked loop circuit that includes a delay replica model unit, a detector for determining the remaining time after subtracting a multiple of a clock cycle from the phase difference between the delay replica clock and the source clock, and a delay locking unit that synchronizes the source clock by delaying it by the detected time to match the phase of the feedback clock, ensuring synchronization within one clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-frequency clock signal is applied to the delay locked loop circuit, then the clock speed increases, but the update time increases and jitter increases
Solution Approach 1:
The delay time adjustment is segmented into multiple discrete stages corresponding to different clock cycle counts (1 cycle, 2 cycles, 3 cycles, etc.). The detector identifies which segment the current phase difference falls into, and the delay locking unit applies the corresponding predetermined delay. This segmentation allows the circuit to handle high-frequency clocks effectively by providing coarse-grained delay adjustment that can be quickly selected without requiring fine-grained adjustments at high speeds.
Solution Approach 2:
The delay locking unit stores multiple predetermined delay times corresponding to different clock cycle counts in advance. When the detector identifies the clock cycle count, the corresponding delay time is already prepared and can be applied immediately without requiring complex real-time calculation or adjustment. This preliminary preparation of delay values enables rapid response to high-frequency clock signals.
2Speed
If a high-frequency clock signal is applied to the delay locked loop circuit, then the clock speed increases, but the jitter increases
Solution Approach 1:
By segmenting the delay adjustment into discrete clock cycle-based stages, the circuit avoids the jitter that would result from attempting continuous or fine-grained delay adjustments at high frequencies. Each segment corresponds to a stable, integer number of clock cycles, ensuring that the phase relationship between source and feedback clocks remains stable and free from sub-cycle jitter.
Solution Approach 2:
The delay time parameter is changed in discrete steps corresponding to integer multiples of clock cycles rather than continuously. This parameter change strategy ensures that the delay adjustment remains synchronized with the clock edges, preventing jitter. The detector and delay locking unit work together to select appropriate discrete delay values that maintain stable phase relationships even at high clock frequencies.
3Speed
If the phase comparator compares phases that are not completely updated, then the circuit operates at high speed, but the synchronization precision decreases
Solution Approach 1:
The phase comparison and delay adjustment process is segmented into clock cycle-based discrete steps. The detector determines which clock cycle count corresponds to the phase difference, and the delay locking unit applies the corresponding predetermined delay. This segmentation allows the system to operate at high speed by using coarse-grained, clock-synchronized measurements rather than requiring complete updates of fine-grained phase information.
Solution Approach 2:
The delay replica model unit generates a copy of the source clock signal that passes through a modeled delay path. This replica clock serves as a reference for the detector to determine the clock cycle count without requiring direct, high-precision measurement of the actual feedback clock phase. The replica provides a simplified, synchronized reference that enables high-speed operation while maintaining sufficient precision for clock cycle-level delay adjustment.
Data Source
AI summary
A delay locked loop circuit includes a delay replica model unit for reflecting a delay time of an actual output path to a source clock and outputting the reflected source clock as a delay replica clock, a detector for detecting a remaining time after subtracting a time corresponding to a multiple of a clock cycle of the source clock from a time corresponding to a phase difference between the delay replica clock and the source clock, and a delay locking unit for delaying the source clock for a delay time to synchronize a clock generated by delaying the source clock for the detected remaining time of the detector with a phase of the source clock.